Slides
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YouTube Videos (click the
 link) |
Chapter 1:
Introduction
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1. Introduction |
Chapter 2: Out-of-order pipelines
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1. Summary of in-order
pipelining
2. Motivation for out-of-order pipelining
3. Register renaming and precise exceptions
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Chatper 3:
The fetch and decode stages
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1. Fetch logic.
2. Branch prediction
3. Decode stage
Notes on operating systems: [pdf]
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Chapter 4:
Issue, execute, commit
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1. Instruction renaming
2. Wakeup, select, and broadcast
3. Load store queue
4. Instruction commit
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Chapter
5: Alternative approaches to issue and commit
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1. Aggressive speculation
2. Replay schemes
3. Compiler based techniques
4. VLIW and EPIC processors |
Chapter 6: Graphics
Processors
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1. Traditional graphics pipeline
2. The CUDA programming language
3. Design of GPGPUs |
Chapter 7:
Caches
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1. Overview of caches
2. Cache optimizations and virtual memory
3. SRAM and CAM arrays
4. Cacti tool, Elmore delay
5. Advanced cache optimizations
6. Trace caches, instruction, and data prefetching |
Chapter 8:
NoC
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1. Network topologies and basic concepts
2. Flow control and flit/packet level switching
3. Routing Algorithms and 5-Stage Router Pipeline
4. Arbiters and Allocators, Pipeline Optimization
5. Non-Uniform Caches, Synthetic Traffic |
Chapter
9: Multicore Systems
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1. Parallel programming and hardware
threads
2. Theoretical foundations
3. Sequential consistency, PLSC, and coherence
4. Execution witnesses, access graphs, causal graphs
5. Cache coherence: snoopy and directory protocols
6. Advanced directory protocols and atomic operations
7. Memory models and data races
8. Methods to detect races
9. Transactional memory |
| Chapter 10: Main Memory |
1. DRAM devices and arrays
2. Synchronous and asynchronous transfer protocols
3. DDR4 states and timing
4. Flash and FeRAMs
5. MRAMs, PCM, ReRAMs and the Roofline model
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| Chapter 11: Power and Temperature |
1. Dynamic and leakage power
2. Temperature modeling
3. Methods to manage power and temperature
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| Chapter 12: Reliability |
1. Soft errors and inductive noise
2. Non-determinism and design faults
3. Process variation, ageing and hard errorrs |
Chapter
13: Secure Architectures
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1. Cryptographic fundamentals and encryption
2. Hashing and secure processors
3. Side channel attacks and oblivious RAM
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Chapter 14:
Architectures for ML
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1. Basic ML Concepts
2. Mathematical representation of CNN computations, stationarity
3. Hardware architectures for 1D/2D convolution
4. Optimizations and memory systems
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