Tutorial

High-level Synthesis for FPGAs

By Dr. Chidamber Kulkarni, Xilinx

Date : 11th Dec

Venue : Room#501, Bharti Building, IIT Delhi

Time : 9:30 AM

Abstract :

High-level synthesis (HLS) has been on the cusp of wider adoption for more than a decade. The benefits of HLS adoption are undisputed, however, the key challenge has been a delicate balance between apt abstraction-level and generation of quality synthesizable code. In recent years, significant progress has been made on delivery of robust and deployable HLS technology. In this tutorial we will introduce key HLS concepts as seen from a FPGA vendor perspective and delve in to the details of a FPGA centric HLS technology, Xilinx AutoESL. We will discuss coding styles and their implications on synthesis results, architecture exploration with a judicious choice of data types, and with the use of a constraint driven synthesis methodology. Finally we will also look in to some current use cases of where HLS technology is becoming immediately useful in FPGA design. Finally we will also discuss future directions for HLS technology and how it can impact FPGA design methodology.