Evaluation plan: Lab 40%, Mid-term 25%, End-term 35%
Attendance: Acadly (Bring your charged phone with acadly installed, Bluetooth and Wifi on)
Attendance policy: standard. Less than 75% attendance means one grade less finally.
Audit pass criteria: No audit. Core course.
Piazza link: col215. Access code is col215 in small letters.
| TA name | Contact |
|---|---|
| Neha | csz238077@cse.iitd.ac.in |
| Deepak Singh | csy257616@cse.iitd.ac.in |
| Sai Kaushik S | csz258470@cse.iitd.ac.in |
| Shreshth Verma | mcs252094@cse.iitd.ac.in |
| Saurabh Joshi | mcs242003@iitd.ac.in |
| Tejaswa Singh Mehra | cs1230133@cse.iitd.ac.in |
| Topic | Slides used in lectures | Textbook chapters |
| Introduction | lecture1.pdf | |
| Transistor, Logic Gates | lecture2.pdf | semiconductor, doping, BJT Transistor, MOSFET Transistor, logic gates using BJT |
| Verilog basics | lecture3_4.pdf | |
| Mid-term Syllabus start | ||
| Representation | lecture_5_6_7.pdf, preeti_representation.pdf | Book Chapter 1 (all sections except 1.8) |
| Boolean algebra, logic gates and minimization | chapter2.pdf, chapter3.pdf | Book Chapter 2 (all sections, except 2.9) and Chapter 3 (all sections, except 3.7, 3.9, 3.10) |
| Combinational Logic | preeti_combinational.pdf, adder.pdf, multiplier-magnitudecomparator.pdf, decoder-multiplexer-encoder.pdf | Book Chapter 4 (till and including practice exercise 4.9. Three state gates onward not in mid-term.) |
| Mid-term revision | midterm-2025.pdf, midterm-2025-answers.pdf, sep9 discussions.pdf | Exercises from Chapters 1-4, Edition 4 solutions are available. |
| Our mid-term exam | ourmidterm.pdf | |
| Mid-term Syllabus end | ||
| Sequential Logic | latch_flipflop.pdf, register.pdf, counter.pdf, sequential_verilog.pdf, fsm_basics.pdf, fsm_verilog.pdf | Book Chapter 5,6 |