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S.No.
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Topics
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Lectures
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Instructor
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References/Notes
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1
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Introduction:
Basic introduction to computers, models, and memory hierarchy.
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01-06
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SDR
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General references on the Internet, [SRS-Basic],
[Patterson-CACM85]
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The von Neumann and
Harvard models. Instructions, memory, ALU, CPU, registers. Who
addresses and access what. Instructions and data for a CPU.
How does a computer boot up? The role of the BIOS/UEFI. How does
a computer identify instructions and data. Given data, how does
it identify signed/unsigned numbers, fixed and floating point numbers.
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25 Jul (Wed) {lecture#SDR-01} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_intro1_20aug24.pdf
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The puzzling question of the range of numbers represented in a
fixed point system. A 4-bit example. Unsigned representation. Signed
representations: signed-bit representation, one's complement
representation for negative integers, two's complement
representation for negative integers.
The pitfalls of finite wordlength effects: under-flow and
over-flow, extreme cases of disasters.
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29 Jul (Tue) {lecture#SDR-02} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_intro2_29jul25.pdf
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How does a computer boot up? (contd.)
Where does an Operating System come in?
Miscellaneous concepts.
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30 Jul (Wed) {lecture#SDR-03} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_intro3_30jul25.pdf
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Modalities for I/O, memory-mapped and direct I/O, ROM.
A gentle introduction to RISC, with history, technological
developments, and basic features.
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01 Aug (Fri) {lecture#SDR-04} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_intro4_01aug25.pdf
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A gentle introduction to RISC (contd): RISC pipelining. A simple
example with 2-stage (general instructions) and 3-stage pipelines
(LOAD/STORE).
Structural, Data and Control hazards, and some
hardware and software solutions.
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05 Aug (Tue) {lecture#SDR-05} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_intro5_05aug25.pdf
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A gentle introduction to RISC (contd): the optimised delayed branch.
Representation of floating point numbers: the IEEE 754
representation.
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06 Aug (Wed) {lecture#SDR-06} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_floating_06aug25.pdf
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2
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Instruction Set Fundamentals: Software and Hardware
The SimpleRISC Instruction Set
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07-11
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SDR
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[SRS-Basic] Chapter 3: Assembly Language.
Section 3.3.
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The SimpleRISC hardware: 15 general-purpose registers including
the stack pointer sp, and the special-purpose return
address register ra. A special register for
programmer-inaccessible flags. The 21-instruction SimpleRISC
instruction set.
1. Register Transfer Instruction mov
2. Arithmetic Instructions
add,
sub,
mul,
div,
mod,
cmp.
3. Logical Instructions
and,
or,
not.
4. Shift Instructions
lsl,
lsr,
asr.
5. Memory Access Instructions
ld,
st.
6. Unconditional Branch Instruction
b.
7. Conditional Branch Instructions
beq,
bgt.
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08 Aug (Fri) {lecture#SDR-07} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_SimpleRISC1_08aug25_12aug25_14aug25.pdf
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8. Subroutine instructions: call and ret.
Taking a step back, and examining the basic philosophy
(`taseer') of
instruction set design: a programming language, encoding it in
hardware, and lastly, designing the circuits to get it working.
It is not a direct mathematical optimisation problem!
9. The nop instruction
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12 Aug (Tue) {lecture#SDR-08} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_SimpleRISC1_08aug25_12aug25_14aug25.pdf
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---
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13 Aug (Wed) {lecture#SDR-xx}
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---
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[No class]
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A non-trivial example of programming in SimpleRISC assembly
language: a recursive subroutine to compute the factorial of a
number. The basic C code, followed by a SimpleRISC assembly version.
Getting back to instruction set design: opcodes, and tweaks.
Inserting a 32-bit number into a register.
Encoding the SimpleRISC instruction set:
1. Encoding 0-address instructions
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14 Aug (Thu) {lecture#SDR-09} 10:00am-11:00am
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SDR
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[hybrid lecture]
moodlenew.iitd.ac.in:
video_SimpleRISC_14aug25.mp4,
lecture_notes_SimpleRISC1_08aug25_12aug25_14aug25.pdf
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2. Encoding 1-address instructions.
Encoding 3-address instructions.
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19 Aug (Tue) {lecture#SDR-10} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_SimpleRISC1_19aug25.pdf
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Encoding cmp, not and mov
instructions.
Encoding the ld and st instructions.
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20 Aug (Wed) {lecture#SDR-11} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_SimpleRISC3_20aug25.pdf
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3
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Arithmetic Circuits
Addition, Multiplication, Division
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11-14
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SDR
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[SRS-Basic] Chapter 8: Computer Arithmetic.
Section 8.1.3.
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Starting with half-adders.
The concept of a (propagation) delay: as clear as...mud.
`It's a jungle out there'. It clearly depends on the
implementation.
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20 Aug (Wed) {lecture#SDR-11} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_arith1_20aug25.pdf
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The effect of variable propagation delays along parallel paths.
Static Hazards: characterisation, removal, and...cases where they
can be useful!
The consensus on standardisation of propagation delays:
`gate-level delay'.
A full adder.
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22 Aug (Fri) {lecture#SDR-12} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_arith2_22aug25.pdf
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The advantages and disadvantages of a Ripple-Carry Adder.
Block operation.
O. J. Bedrij's `Carry Select Adder': faster addition at the cost
of more hardware. Two stages of computation, and the overall
O(\sqrt(n)) time complexity.
The Carry Look-Ahead Adder: the irritating C_{out}
computation takes two gate delay levels, with multi-input AND and
OR gates.
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24 Aug (Sun) {lecture#SDR-13} 08:00am-09:00am
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SDR
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[Online-only class: 08:00am-09:00am]
(Make-up class for the missed 13 Aug (Wed) class)
moodlenew.iitd.ac.in:
video_arith3_24aug25.mp4,
lecture_notes_arith3_24aug25.pdf
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This should be O(1)...however, fan-in restrictions!
Derivation of the O(log n) time complexity: the two-phase
design.
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26 Aug (Tue) {lecture#SDR-14} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_arith4_26aug25.pdf
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4
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Processor Design
Instruction Processing Pipeline
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14-19
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SDR
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[SRS-Basic]
Chapter 9: Processor Design. Section 9.2.
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The 5 units of a SimpleRISC instruction pipeline. A `Register File'.
The concept of a `bus'.
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26 Aug (Tue) {lecture#SDR-14} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_processor_design1_26aug25.pdf
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Control and Data paths. A nice hardware hack: a biphasic clock.
Design of the following units: Fetch Unit, Operand Fetch Unit.
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27 Aug (Wed) {lecture#SDR-15} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_processor_design2_27aug25.pdf
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Reading the registers.
The Execute Unit.
The ALU.
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29 Aug (Fri) {lecture#SDR-16} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_processor_design3_29aug25.pdf
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The ALU (contd).
The Memory access Unit.
The Register Write-Back Unit.
Putting it all together!
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30 Aug (Sat) {lecture#SDR-17} 06:00am-07:00am
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SDR
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[Online-only class: 06:00am-07:00am]
moodlenew.iitd.ac.in:
video_processor_design4_30aug25.mp4,
lecture_notes_processor_design4_30aug25.pdf
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A step back, to understand what op1 and
op2 are, in the SimpleRISC processor design.
The hardwired control unit.
Microprogramming: the 1995 Intel Pentium story.
An old 1960s concept! Plus and minus points.
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31 Aug (Sun) {lecture#SDR-18} 06:00am-07:00am
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SDR
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[Online-only class: 06:00am-07:00am]
(Make-up class for the 10 Sep (Wed) class to be missed)
moodlenew.iitd.ac.in:
video_processor_design5_31aug25.mp4,
lecture_notes_processor_design5_31aug25.pdf
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Microprogramming in a new avatAr.
`flashing' of a processor/`firmware update'.
Three manifestations of the same: the Intel story (translation table),
SoC and Custom diagnostic routines such as BIST. An important
concept in microprogrammed processors: the crucial role of a bus.
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01 Sep (Mon) {lecture#SDR-19} 07:30pm-08:30pm
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SDR
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[Online-only class: 07:30pm-08:30pm]
(Make-up class for the 02 Sep (Tue) class to be missed)
moodlenew.iitd.ac.in:
video_processor_design6_pipelining1_01sep25.mp4,
lecture_notes_processor_design6_01sep25.pdf,
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5
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Principles of Pipelining
Basic Concepts of Pipeline, for SimpleRISC
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19-21
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SDR
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[SRS-Basic]
Chapter 10: Principles of Pipelining.
Sections 10.2
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The 5-stage SimpleRISC pipeline, with `latches' in between stages.
Basic concept of an `instruction packet'. The IF and OF stages,
with the instruction packet.
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01 Sep (Mon) {lecture#SDR-19} 07:30pm-08:30pm
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SDR
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[Online-only class: 07:30pm-08:30pm]
(Make-up class for the 02 Sep (Tue) class to be missed)
moodlenew.iitd.ac.in:
video_processor_design6_pipelining1_01sep25.mp4,
lecture_notes_pipelining1_01sep25.pdf
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---
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02 Sep (Tue) {lecture#SDR-xx} 10:00am-11:00am
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---
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[No class]
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---
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03 Sep (Wed) {lecture#SDR-xx} 10:00am-11:00am
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---
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[No class]
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The EX, MA and RW stages with the instruction packet.
Hazards and pipeline diagrams (space-time diagrams).
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07 Sep (Sun) {lecture#SDR-20} 08:00am-09:00am
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SDR
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[Online-only class: 08:00am-09:00am]
(Make-up class for the 03 Sep (Wed) class to be missed)
moodlenew.iitd.ac.in:
video_pipelining2_07sep25.mp4,
lecture_notes_pipelining2_07sep25.pdf
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Two ways to implement a `bubble'.
`Forwarding', to make matters a little efficient.
Small notes: interrupts, privileged instructions,
`green computing' is an oxymoron! multiple issue in-order
pipelines: EPIC/VLIW, OOO (out-of-order) pipelines.
Register renaming.
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09 Sep (Tue) {lecture#SDR-21} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_pipelining3_09sep25.pdf
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---
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10 Sep (Wed) {lecture#SDR-xx} 10:00am-11:00am
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---
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[No class]
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Mid-Term
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16 Sep (Tue) 10:30am-12:30pm, LH-108/LH-111/LH-114/LH-121.
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SDR
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Please check the room number and exact seat number by logging in
to https://exam.iitd.ac.in/
Please note that this mapping is visible only a few hours before
the actual examination.
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6
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Caches
Basic Concepts of Caches, for RISC Pipelines
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22-24
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SDR
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[HP5, HP6] Cache Basics: Appendix B: Review of Memory Hierarchy.
Sections B.1 and B.2
Multiprocessor Cache Coherence: Chapter 5: Thread-Level
Parallelism. Sections 5.1 and 5.2
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Getting the strategy `write': write-back and write-through.
write-allocate and no-write-allocate.
Multi-processor Cache Coherence: The Write-Invalidate Protocol, a
snooping protocol.
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11 Nov (Tue) {lecture#SDR-22} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_cache1_11nov25.pdf
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The Write Invalidate Protocol, in all its gory details (contd).
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12 Nov (Wed) {lecture#SDR-23} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_cache2_12nov25.pdf
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A loaded numerical involving split and unified cache, involving
the average miss rate, and the average memory access time.
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14 Nov (Fri) {lecture#SDR-24} 10:00am-11:00am
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SDR
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moodlenew.iitd.ac.in:
lecture_notes_cache3_14nov25.pdf
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