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S.No.
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Topics
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Lectures
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Instructor
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References/Notes
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1
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Introduction:
Basic introduction to memory hierarchy.
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01-03
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SDR
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The von Neumann and
Harvard models. Instructions, memory, ALU, CPU, registers. Who
addresses and access what. Instructions and data for a CPU.
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20 Aug (Tue) {lecture#SDR-01} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_intro1_20aug24.mp4,
lecture_notes_intro1_20aug24.pdf
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How does a computer boot up? (contd.)
Where does an Operating System come in?
Miscellaneous concepts.
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21 Aug (Wed) {lecture#SDR-02} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_intro2_21aug24.mp4,
lecture_notes_intro2_21aug24.pdf
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Modalities for I/O, memory-mapped and direct I/O, ROM.
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23 Aug (Fri) {lecture#SDR-03} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_intro3_cache1_23aug24.mp4,
lecture_notes_intro3_23aug24.pdf
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2
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Caches
Types and Designs, Multiprocessor systems.
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03-09
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SDR
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[HP5, HP6] Cache Basics: Appendix B: Review of Memory Hierarchy.
Sections B.1 and B.2
Multiprocessor Cache Coherence: Chapter 5: Thread-Level
Parallelism. Sections 5.1 and 5.2
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The memory hierarchy. What is a cache, and what is the role of a
cache. The need for a cache, predictions.
The special role of a cache for DSPs: caching data and instructions.
The Harvard Architecture for caches.
Caches for general purpose processors.
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23 Aug (Fri) {lecture#SDR-03} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_intro3_cache1_23aug24.mp4,
lecture_notes_cache1_23aug24.pdf
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The four basic cache questions. Cache organisation: direct
mapped, fully associative and set associative. Cache and memory
blocks, and address spaces.
Cache block replacement: LRU, and alternatives.
Cache write strategies: Write-Through and Write-Back. Advantages
and disadvantages of each.
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27 Aug (Tue) {lecture#SDR-04} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache2_27aug24.mp4,
lecture_notes_cache2_27aug24.pdf
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Write Allocate and No Write Allocate: an introduction.
An example of Write Allocate and No Write Allocate.
Some RISC basics. Structural Hazards.
Cache operation: a complete (loaded!) numerical example with split and
unified caches. This will illustrate basics of cache operations,
and practical issues with split and unified caches.
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28 Aug (Wed) {lecture#SDR-05} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache3_28aug24.mp4,
lecture_notes_cache3_28aug24.pdf
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Cache operation: the complete (loaded!) numerical example with split and
unified caches (contd).
Introduction to Multiprocessor Cache Coherence. Centralised
shared memory architectures. Snooping Protocols: The popular
Write Invalidate Protocol. Issues and basic philosophy. The three
possible states of a cache block.
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30 Aug (Fri) {lecture#SDR-06} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache4_30aug24.mp4,
lecture_notes_cache4_30aug24.pdf
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03 Sep (Tue) {lecture#TKG-11} 10:00am-11:00am
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TKG
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The Write Invalidate Protocol, in all its gory details (contd).
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04 Sep (Wed) {lecture#SDR-07} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache5_04sep24.mp4, lecture_notes_cache5_04sep24.pdf
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06 Sep (Fri) {lecture#TKG-12} 10:00am-11:00am
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TKG
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10 Sep (Wed) {lecture#TKG-13} 10:00am-11:00am
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TKG
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11 Sep (Wed) {lecture#TKG-14} 10:00am-11:00am
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TKG
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MidTerm-1
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17 Sep (Tue) 10:30am-12:30pm
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TKG
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The Write Invalidate Protocol, in all its gory details (contd).
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20 Sep (Fri) {lecture#SDR-08} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache6_vm1_20sep24.mp4,
lecture_notes_cache6_vm1_20sep24.pdf
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3
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Memory:
Virtual Memory.
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10-11
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SDR
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[HP5, HP6] Virtual Memory: Appendix B: Review of Memory Hierarchy. Section B.4
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Introduction to Virtual Memory: Paging and Segmentation
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20 Sep (Fri) {lecture#SDR-08} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache6_vm1_20sep24.mp4,
lecture_notes_cache6_vm1_20sep24.pdf
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Introduction to Virtual Memory: Paging and Segmentation (contd).
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24 Sep (Tue) {lecture#SDR-09} 10:00am-11:00am
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SDR
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4
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Some aspects of RISC:
Hazards, RISC characteristics, RISC
optimisation.
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09-11
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SDR
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[HP5, HP6] Virtual Memory: Appendix B: Review of Memory Hierarchy. Section B.4
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Some basic characteristics of RISC processors, RISC pipelines.
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24 Sep (Tue) {lecture#SDR-09} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_vm2_risc1_24sep24.mp4, lecture_notes_vm2_risc1_24sep24.pdf
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Simple RISC pipelines: hazards (data, structural, control).
The delayed brach. The optimised delayed branch.
Introduction to static pipeline scheduling: a loaded example.
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25 Sep (Wed) {lecture#SDR-10} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_risc2_25sep24.mp4, lecture_notes_risc2_25sep24.pdf
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Basic pipeline scheduling and loop unrolling.
An example of a C loop translated to basic MIPS assembly code.
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26 Sep (Thu) {lecture#SDR-11}
08:30pm-09:08pm [Online-Only Class]
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SDR
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MS-Teams folder:
video_risc3_26sep24.mp4,
lecture_notes_risc3_26sep24.pdf
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---
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01 Oct (Tue) {lecture#SDR-11} 10:00am-11:00am
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(No Class)
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---
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Loop unrolling. Loop unrolling with scheduling.
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04 Oct (Fri) {lecture#SDR-12} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_risc4_pipeline1_04oct24.mp4,
lecture_notes_risc4_pipeline1_04oct24.pdf
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5
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Some pipelining theory:
Parameters, Static and Dynamic Scheduling,
Optimisation.
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12-14
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SDR
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[P. Kogge]
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Parameters: Clock period/frequency, Speedup, Efficiency, Pipeline
throughput. The concept of a reservation table as a function.
Collisions. Compute time. Static and Dynamic pipelines.
Examples: Reservation Table A and Reservation Table B.
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04 Oct (Fri) {lecture#SDR-12} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_risc4_pipeline1_04oct24.mp4,
lecture_notes_risc4_pipeline1_04oct24.pdf
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The depressing worst-case bound: exponential.
The MAL Lemma (Lemma 3-1), and its (easy) proof. The need for a
better (more compact) representation, than a reservation table:
Collision Vectors. State diagrams (modified state diagrams,
actually). FSM modelling of the pipeline scheduling problem.
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15 Oct (Tue) {lecture#SDR-13} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_pipeline2_15oct24.mp4,
lecture_notes_pipeline2_15oct24.pdf
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Lemma 3-2: finding simple cycles suffices. Lemma 3-3: the upper
bound. Proof of both. The combined lemmas, and the best and worst
case scenarios.
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16 Oct (Wed) {lecture#SDR-14} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_pipeline3_16oct24.mp4,
lecture_notes_pipeline3_16oct24.pdf
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MidTerm-2
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18 Oct (Fri) 06:00pm-07:30pm
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SDR
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[Paper-and-pen exam, as described in the relevant email]
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