|
S.No.
|
Topics
|
Lectures
|
Instructor
|
References/Notes
|
|
1
|
Introduction:
Basic introduction to computers, models, and memory hierarchy.
|
01-09
|
SDR
|
General references on the Internet, [SRS-Basic] (number systems),
[Patterson-CACM85] (RISC),
[HP5, HP6] (RISC pipeline scheduling)
|
|
|
The von Neumann and
Harvard models. Instructions, memory, ALU, CPU, registers. Who
addresses and access what. Instructions and data for a CPU.
How does a computer boot up? The role of the BIOS/UEFI.
|
24 Jul (Fri) {lecture#SDR-01} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_intro1_24jul26.pdf
|
|
|
How does a computer boot up? (contd.)
RAM and ROM.
|
28 Jul (Tue) {lecture#SDR-02} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
|
|
|
How does
a computer identify instructions and data. Given data, how does
it identify signed/unsigned numbers, fixed and floating point numbers.
How does a computer boot up? (contd.)
|
29 Jul (Wed) {lecture#SDR-03} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_intro2_29jul25.pdf
|
|
|
The puzzling question of the range of numbers represented in a
fixed point system. A 4-bit example. Unsigned representation. Signed
representations: signed-bit representation, one's complement
representation for negative integers, two's complement
representation for negative integers.
The pitfalls of finite wordlength effects: under-flow and
over-flow, extreme cases of disasters.
How a computer boots up (contd).
Where does an Operating System
come in? Miscellaneous concepts.
|
29 Jul (Wed) {lecture#SDR-04} 10:00pm-11:00pm
|
SDR
|
[Online-only class: 10:00pm-11:00pm]
(Make-up class for the 31 Jul (Fri) class to be missed)
moodlenew.iitd.ac.in:
video_intro3_29jul26.mp4,
lecture_notes_intro3_29jul25.pdf
|
|
|
---
|
31 Jul (Fri) {lecture#xxx-xxx} 10:00am-11:00am
|
---
|
[No class]
|
|
|
Modalities for I/O, memory-mapped and direct I/O, ROM.
A soft introduction to pipelining.
A gentle introduction to RISC, with some history.
technological
developments, and basic features.
|
02 Aug (Sun) {lecture#SDR-05} 10:00am-11:00am
|
SDR
|
[Online-only class: 10:00am-11:00am]
(Make-up class for the 12 Aug (Wed) class to be missed)
moodlenew.iitd.ac.in:
video_intro4_02aug26.mp4,
lecture_notes_intro4_02aug26.pdf
|
|
|
RISC pipelining. A simple example with 2-stage (general instructions)
and 3-stage pipelines
(LOAD/STORE).
Structural, Data and Control hazards, and some
hardware and software solutions.
|
03 Aug (Mon) {lecture#SDR-06} 09:30pm-10:30pm
|
SDR
|
[Online-only class: 09:30pm-10:30pm]
(Make-up class for the 21 Aug (Fri) class to be missed)
moodlenew.iitd.ac.in:
video_intro5_03aug26.mp4,
lecture_notes_intro5_03aug26.pdf
|
|
|
Structural, Data and Control hazards, and some hardware and
software solutions (contd). The optimised delayed branch.
Introduction to static pipeline scheduling: a loaded example.
|
04 Aug (Tue) {lecture#SDR-07} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_intro6_04aug26.pdf
|
|
|
Introduction to static pipeline scheduling: a loaded example.
Basic pipeline scheduling and loop unrolling. An example of a C
loop translated to basic MIPS assembly code.
Loop unrolling. Loop unrolling with scheduling.
|
05 Aug (Wed) {lecture#SDR-08} 10:00am-11:00am
|
SDR
|
[HP6] Chapter 3, Section 3.2
moodlenew.iitd.ac.in:
lecture_notes_intro7_05aug26.pdf
|
|
|
Representation of floating point numbers: the IEEE 754
representation.
|
07 Aug (Fri) {lecture#SDR-09} 10:00am-11:00am
|
SDR
|
[HP6] Chapter 3, Section 3.2
moodlenew.iitd.ac.in:
lecture_notes_floating_07aug26.pdf
|
|
2
|
Instruction Set Fundamentals: Software and Hardware
The SimpleRISC Instruction Set
|
09-13
|
SDR
|
[SRS-Basic] Chapter 3: Assembly Language.
Section 3.3.
|
|
|
The SimpleRISC hardware: 15 general-purpose registers including
the stack pointer sp, and the special-purpose return
address register ra. A special register for
programmer-inaccessible flags. The 21-instruction SimpleRISC
instruction set.
1. Register Transfer Instruction mov
2. Arithmetic Instructions
add,
sub,
mul,
div,
mod,
cmp.
3. Logical Instructions
and,
or,
not.
4. Shift Instructions
lsl,
lsr,
asr.
5. Memory Access Instructions
ld,
st.
6. Unconditional Branch Instruction
b.
7. Conditional Branch Instructions
beq,
bgt.
8. Subroutine instructions: call and ret.
9. The nop instruction
|
07 Aug (Fri) {lecture#SDR-09} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_SimpleRISC1_07aug26.pdf
|
|
|
Taking a step back, and examining the basic philosophy
(`tAseer') of
instruction set design: a programming language, encoding it in
hardware, and lastly, designing the circuits to get it working.
It is not a direct mathematical optimisation problem!
More about the instruction set as a software programmer: an
assembly language for programming.
|
11 Aug (Tue) {lecture#SDR-10} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_SimpleRISC2_11aug26.pdf
|
|
|
---
|
12 Aug (Wed) {lecture#SDR-xx}
|
---
|
[No class]
|
|
|
A non-trivial example of programming in SimpleRISC assembly
language: a recursive subroutine to compute the factorial of a
number. The basic C code, followed by a SimpleRISC assembly version.
|
14 Aug (Fri) {lecture#SDR-11} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_SimpleRISC3_14aug26.pdf
|
|
|
A non-trivial example of programming in SimpleRISC assembly
language (contd).
Getting back to instruction set design: opcodes, and tweaks.
Inserting a 32-bit number into a register.
Encoding the SimpleRISC instruction set:
1. Encoding 0-address instructions
2. Encoding 1-address instructions.
Encoding 3-address instructions.
|
18 Aug (Tue) {lecture#SDR-12} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_SimpleRISC4_18aug26.pdf
|
|
|
Encoding 3-address instructions (contd)
Encoding cmp, not and mov
instructions.
Encoding the ld and st instructions.
|
19 Aug (Wed) {lecture#SDR-13} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_SimpleRISC5_19aug26.pdf
|
|
3
|
Arithmetic Circuits
Addition, Multiplication, Division
|
14-15
|
SDR
|
[SRS-Basic] Chapter 8: Computer Arithmetic.
Section 8.1.3.
|
|
|
---
|
21 Aug (Fri) {lecture#SDR-xx}
|
---
|
[No class]
|
|
|
Starting with half-adders.
The concept of a (propagation) delay: as clear as...mud.
`It's a jungle out there'. It clearly depends on the
implementation.
The effect of variable propagation delays along parallel paths.
Static Hazards: characterisation, removal, and...cases where they
can be useful!
The consensus on standardisation of propagation delays:
`gate-level delay'.
A full adder.
|
25 Aug (Tue) {lecture#SDR-14} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_arith1_25aug26.pdf
|
|
|
The advantages and disadvantages of a Ripple-Carry Adder.
Block operation.
O. J. Bedrij's `Carry Select Adder': faster addition at the cost
of more hardware. Two stages of computation, and the overall
O(\sqrt(n)) time complexity.
The Carry Look-Ahead Adder: the irritating C_{out}
computation takes two gate delay levels, with multi-input AND and
OR gates.
This should be O(1)...however, fan-in restrictions!
Derivation of the O(log n) time complexity: the two-phase
design.
|
28 Aug (Fri) {lecture#SDR-15} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_arith2_28aug26.pdf
|
|
4
|
Processor Design
Instruction Processing Pipeline
|
15-18
|
SDR
|
[SRS-Basic]
Chapter 9: Processor Design. Section 9.2.
|
|
|
The 5 units of a SimpleRISC instruction pipeline. A `Register File'.
The concept of a `bus'.
Control and Data paths. A nice hardware hack: a biphasic clock.
Design of the Fetch Unit.
|
28 Aug (Fri) {lecture#SDR-15} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_processor_design1_28aug26.pdf
|
|
|
Design of the Operand Fetch Unit.
Reading the registers.
The Execute Unit.
The ALU.
The Memory access Unit.
The Register Write-Back Unit.
|
29 Aug (Sat) {lecture#SDR-16} 10:00am-11:00am
|
SDR
|
[Online-only class: 10:00am-11:00am]
(Make-up class for the 02 Sep (Wed) class to be missed)
moodlenew.iitd.ac.in:
video_processor_design2_29aug26.mp4,
lecture_notes_processor_design2_29aug26.pdf
|
|
|
Putting it all together!
A step back, to understand what op1 and
op2 are, in the SimpleRISC processor design.
The hardwired control unit.
|
01 Sep (Tue) {lecture#SDR-17} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_processor_design3_01sep26.pdf
|
|
|
---
|
02 Sep (Wed) {lecture#SDR-xx}
|
---
|
[No class]
|
|
|
---
|
03 Sep (Thu) {lecture#SDR-xx}
|
---
|
[No class]
|
|
|
Microprogramming: the 1995 Intel Pentium story.
An old 1960s concept! Plus and minus points.
Microprogramming in a new avatAr.
`flashing' of a processor/`firmware update'.
Three manifestations of the same: the Intel story (translation table),
SoC and Custom diagnostic routines such as BIST. An important
concept in microprogrammed processors: the crucial role of a bus.
|
05 Sep (Sat) {lecture#SDR-18} 09:30am-10:30am
|
SDR
|
[Online-only class: 09:30am-10:30am]
(Make-up class for the 03 Sep (Thu) missed class)
moodlenew.iitd.ac.in:
video_processor_design4_pipelining1_05sep26.mp4,
lecture_notes_processor_design4_05sep26.pdf
|
|
5
|
Principles of Pipelining
Basic Concepts of Pipeline, for SimpleRISC
|
18-19
|
SDR
|
[SRS-Basic]
Chapter 10: Principles of Pipelining.
Sections 10.2
|
|
|
The 5-stage SimpleRISC pipeline, with `latches' in between stages.
Basic concept of an `instruction packet'. The IF and OF stages,
with the instruction packet.
The EX, MA and RW stages with the instruction packet.
Hazards and pipeline diagrams (space-time diagrams).
|
05 Sep (Sat) {lecture#SDR-18} 09:30am-10:30am
|
SDR
|
[Online-only class: 09:30am-10:30am]
(Make-up class for the 03 Sep (Thu) missed class)
moodlenew.iitd.ac.in:
video_processor_design4_pipelining1_05sep26.mp4,
lecture_notes_processor_design4_05sep26.pdf
|
|
|
Two ways to implement a `bubble'.
`Forwarding', to make matters a little efficient.
Small notes: interrupts, privileged instructions,
`green computing' is an oxymoron! multiple issue in-order
pipelines: EPIC/VLIW, OOO (out-of-order) pipelines.
Register renaming.
|
08 Sep (Tue) {lecture#SDR-19} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_pipelining2_08sep26.pdf
|
|
6
|
Caches
Basic Concepts of Caches, for RISC Pipelines
|
20-20
|
SDR
|
[HP5, HP6] Cache Basics: Appendix B: Review of Memory Hierarchy.
Sections B.1 and B.2
Multiprocessor Cache Coherence: Chapter 5: Thread-Level
Parallelism. Sections 5.1 and 5.2
|
|
|
Introduction to caches: types. Four basic cache questions.
Trying to answer the first two.
|
09 Sep (Wed) {lecture#SDR-20} 10:00am-11:00am
|
SDR
|
moodlenew.iitd.ac.in:
lecture_notes_cache_09sep26.pdf
|
|
|
Mid-Term
|
Mid-Term: 16 Sep (Wed) 10:30am-12:30pm, LH-108/111/114/121
|
SDR
|
Please check the room number and exact seat number by logging in
to https://exam.iitd.ac.in/
Please note that this mapping is visible only a few hours before
the actual examination.
|