Computer Architecture [UG] (ELL305)

The course is to be jointly taught by Tapan K. Gandhi, Sumantra and Subrat Kar
This page houses the part to be covered by the second instructor, Sumantra.


General Information

Apart from those who have to take this courses as a Program Core (PC), people are also welcome to sit through the course.

Credits: 3 (LTP: 3-0-0) [Slot E]

Schedule for Classes:

Tuesday
10:00 - 11:00
LH-114
Wednesday
10:00 - 11:00
LH-114
Friday
10:00 - 11:00
LH-114

Schedule for Examination:

Additional Minor: 18 Oct (Tue) 07:00pm-08:00pm. Venue: LH-121 Upload deadline on gradescope: 08:00pm.

Teaching Assistants: 


Books, Papers and other Documentation

Basic Texts:

Reference Books:


Lecture Schedule, Links to Material (where applicable)

Please see the link to the I Sem (Autumn) 2021-2022 offering of this course, for an idea of the approximate structure of the course.
S.No.
Topics
Lectures
Instructor
References/Notes
1
Introduction:
Basic introduction to memory hierarchy.
01-02
SDR
The von Neumann and Harvard models. Instructions, memory, ALU, CPU, registers. Who addresses and access what. Instructions and data for a CPU.
03 Sep (Sat) {lecture#SDR-01} 10:00am-11:00am
SDR
[Online-only class: MS-Teams: 10:00am-11:00am] (Make-up class for the 06 Sep (Tue) class to be missed)

MS-Teams folder: video_intro1_03sep22.mp4, lecture_notes_intro1_03sep22.pdf
How does a computer boot up? (contd.) Where does an Operating System come in?
04 Sep (Sun) {lecture#SDR-02} 10:00am-11:00am
SDR
[Online-only class: MS-Teams: 10:00am-11:00am] (Make-up class for the 07 Sep (Wed) class to be missed)

MS-Teams folder: video_intro2_cache1_04sep22.mp4, lecture_notes_intro2_cache1_04sep22.pdf
2
Caches
Types and Designs, Multiprocessor systems.
02-06
SDR
[HP5, HP6] Cache Basics: Appendix B: Review of Memory Hierarchy. Sections B.1 and B.2 Multiprocessor Cache Coherence: Chapter 5: Thread-Level Parallelism. Sections 5.1 and 5.2
The memory hierarchy. What is a cache, and what is the role of a cache. The need for a cache, predictions.
04 Sep (Sun) {lecture#SDR-02} 10:00am-11:00am
SDR
[Online-only class: MS-Teams: 10:00am-11:00am] (Make-up class for the 07 Sep (Wed) class to be missed)

MS-Teams folder: video_intro2_cache1_04sep22.mp4, lecture_notes_intro2_cache1_04sep22.pdf
The special role of a cache for DSPs: caching data and instructions. The Harvard Architecture for caches. Caches for general purpose processors. The four basic cache questions. Cache organisation: direct mapped, fully associative and set associative. Cache and memory blocks, and address spaces.
09 Sep (Fri) {lecture#SDR-03} 10:00am-11:00am
SDR
MS-Teams folder: video_cache2_09sep22.mp4, lecture_notes_cache2_09sep22.pdf
In detail: the three cache organisations: direct mapped, fully associative and set associative. Cache block replacement: LRU, and alternatives.
11 Sep (Sun) {lecture#SDR-04} 08:00am-09:00am
SDR

[Online-only class: 08:00am-09:00am]
(Make-up class for the 16 Sep (Fri) class to be missed)


MS-Teams folder: video_cache3_11sep22.mp4, lecture_notes_cache3_11sep22.pdf
Cache write strategies: Write-Through and Write-Back. Advantages and disadvantages of each. Write Allocate and No Write Allocate: an introduction. Cache write strategies: Write-Through and Write-Back (contd). Advantages and disadvantages of each. Write Allocate and No Write Allocate: an introduction.
13 Sep (Tue) {lecture#SDR-05} 10:00am-11:00am
SDR


MS-Teams folder: video_cache4_13sep22.mp4, lecture_notes_cache4_13sep22.pdf
An example of Write Allocate and No Write Allocate. Cache operation: a complete (loaded!) numerical example with split and unified caches. This will illustrate basics of cache operations, and practical issues with split and unified caches. Cache operation: a complete (loaded!) numerical example with split and unified caches (contd.).
14 Sep (Wed) {lecture#SDR-06} 10:00am-11:00am
SDR
MS-Teams folder: video_cache5_14sep22.mp4, lecture_notes_cache5_14sep22.pdf
A brief digression to understand the basic concepts of RISC pipelining, which are relevant to this example.

Introduction to Multiprocessor Cache Coherence. Centralised shared memory architectures. Snooping Protocols: The popular Write Invalidate Protocol. Issues and basic philosophy. The three possible states of a cache block. The Write Invalidate Protocol, in all its gory details.
20 Sep (Tue) {lecture#SDR-07} 10:00am-11:00am
SDR
MS-Teams folder: video_cache6_20sep22.mp4, lecture_notes_cache6_20sep22.pdf
The Write Invalidate Protocol, in all its gory details (contd).
21 Sep (Wed) {lecture#SDR-08} 10:00am-11:00am
SDR
MS-Teams folder: video_cache7_21sep22.mp4, lecture_notes_cache7_21sep22.pdf
The Write Invalidate Protocol, in all its gory details (contd).
23 Sep (Fri) {lecture#SDR-09} 10:00am-11:00am
SDR
MS-Teams folder: video_cache8_vm1_23sep22.mp4, lecture_notes_cache8_vm1_23sep22.pdf
3
Memory:
Virtual Memory.
10-11
SDR
[HP5, HP6] Virtual Memory: Appendix B: Review of Memory Hierarchy. Section B.4
Introduction to Virtual Memory: Paging and Segmentation
23 Sep (Fri) {lecture#SDR-09} 10:00am-11:00am
SDR
MS-Teams folder: video_cache8_vm1_23sep22.mp4, lecture_notes_cache8_vm1_23sep22.pdf
Paging and Segmentation (contd).
07 Oct (Fri) {lecture#SDR-10} 10:00am-11:00am
SDR
MS-Teams folder: video_vm2_07oct22.mp4, lecture_notes_vm2_07oct22.pdf
Paging and Segmentation (contd).

A little follow-up on RISC pipelining: overcoming hazards through static scheduling, to alleviate cases of data hazards and control hazards.
08 Oct (Sat) {lecture#SDR-11} 10:00am-11:00am
SDR
MS-Teams folder: video_vm3_risc_08oct22.mp4, lecture_notes_vm3_risc_08oct22.pdf
Additional Minor
18 Oct (Tue) 07:00pm-08:00pm. Upload deadline on gradescope: 08:00pm.
SDR
[Paper-and-pen exam, as described in the relevant email]
The above list is (obviously!) not exhaustive. Other reference material will be announced in the class. The Web has a vast storehouse of tutorial material on Computer Organisation/Architecture other related areas.

Examinations and Grading Information

The marks distribution is as follows (out of a total of 100):
Additional Minor
32 (SDR)

Attendance Requirements:

Attendance requirements: according to the IITD policy for Online Semesters
Illness policy: illness to be certified by a registered medical practioner.
Attendance in Examinations is Compulsory.


Course Feedback

Link to Course Feedback Form
Tapan K. Gandhi, Sumantra Dutta Roy, Subrat Kar Department of Electrical Engineering, IIT Delhi, Hauz Khas,
New Delhi - 110 016, INDIA. tgandhi@ee.iitd.ac.in, sumantra@ee.iitd.ac.in, subrat@ee.iitd.ac.in