The overall objective of my research
is to accelerate high-performance computing (HPC) applications using existing hardware
accelerators and then design new re- configurable fabrics to
achieve further speedup.
Accelerator technology has become very popular in the community
in the past decade. Typically hardware accelerators
support the main processor in order to carry out the compute
intensive tasks. The accelerators differ in target
technology as well as in their core architectures. Popular
implementations are based on Field Programmable Gate Arrays
(FPGAs), Graphics Processor Units (GPUs), Application Specific
Integrated Circuits (ASICs), CELL apart from some other
miscellaneous approaches. Current FPGAs contain multiplier,
memory units and even processors embedded in them to give better
performance. My research interest is to develop domain specific
re-configurable accelerators for speeding up HPC applications.
In order to come up with such domain specific accelerators
proper design space exploration needs to be carried out at a
higher level. I work with my supervisors to develop
methodologies to enable this design space exploration.
Publications:
1. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier:
“Hardware Acceleration of De Novo Genome Assembly”, Integration, the VLSI Journal, (submitted Aug-2013)