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S.No.
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Topics
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Lectures
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Instructor
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References/Notes
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1
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Introduction:
Basic introduction to memory hierarchy.
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01-01
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SDR
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The von Neumann and
Harvard models. Instructions, memory, ALU, CPU, registers. Who
addresses and access what. Instructions and data for a CPU. What
is a cache, and what is the role of a cache.
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10 Sep (Fri) {lecture#SDR-01} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_intro_10sep21.mp4,
lecture_notes_intro_10sep21.pdf
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2
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Caches
Types and Designs, Multiprocessor systems.
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01-06
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SDR
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[HP5, HP6] Cache Basics: Appendix B: Review of Memory Hierarchy.
Sections B.1 and B.2
Multiprocessor Cache Coherence: Chapter 5: Thread-Level
Parallelism. Sections 5.1 and 5.2
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The need for a cache, predictions. The special role of a cache
for DSPs: caching data and instructions. Cache and memory blocks,
and address spaces. The four basic cache questions. Cache
organisation: direct mapped, fully associative and set
associative.
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14 Sep (Tue) {lecture#SDR-02} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache1_14sep21.mp4,
lecture_notes_cache1_14sep21.pdf
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In detail: the three cache organisations: direct mapped, fully
associative and set associative. Cache block replacement: LRU,
and alternatives. Cache write strategies: Write-Through and
Write-Back. Advantages and disadvantages of each. Write Allocate
and No Write Allocate: an introduction.
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15 Sep (Wed) {lecture#SDR-03} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache2_15sep21.mp4, lecture_notes_cache2_15sep21.pdf
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Cache write strategies: Write-Through and Write-Back (contd).
Advantages and disadvantages of each. Write Allocate
and No Write Allocate: an introduction.
An example of Write Allocate and No Write Allocate.
Cache operation: a complete (loaded!) numerical example with split and
unified caches. This will illustrate basics of cache operations,
and practical issues with split and unified caches.
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17 Sep (Fri) {lecture#SDR-04} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache3_17sep21.mp4, lecture_notes_cache3_17sep21.pdf
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Cache operation: a complete (loaded!) numerical example with split and
unified caches (contd.). A brief digression to understand the
basic concepts of RISC pipelining, which are relevent to this
example.
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24 Sep (Fri) {lecture#SDR-05} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache4_24sep21.mp4, lecture_notes_cache4_24sep21.pdf
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Cache operation: a complete (loaded!) numerical example with split and
unified caches (contd.).
Introduction to Multiprocessor Cache Coherence.
Centralised shared memory architectures. Snooping Protocols: The
popular Write Invalidate Protocol.
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25 Sep (Sat) {lecture#SDR-06} 08:00am-09:00am
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SDR
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MS-Teams folder:
video_cache5_25sep21.mp4, lecture_notes_cache5_25sep21.pdf
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The Write Invalidate Protocol (contd).
Issues and basic philosophy.
The three possible states of a cache block.
The Write Invalidate Protocol, in all its gory details.
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28 Sep (Tue) {lecture#SDR-07} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache6_28sep21.mp4, lecture_notes_cache6_28sep21.pdf
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The Write Invalidate Protocol, in all its gory details (contd).
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29 Sep (Wed) {lecture#SDR-08} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache7_29sep21.mp4, lecture_notes_cache7_29sep21.pdf
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The Write Invalidate Protocol, in all its gory details (contd).
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01 Oct (Fri) {lecture#SDR-09} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache8_vm1_01oct21.mp4,
lecture_notes_cache8_vm1_01oct21.pdf
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3
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Memory:
Virtual Memory.
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10-11
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SDR
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[HP5, HP6] Virtual Memory: Appendix B: Review of Memory Hierarchy. Section B.4
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Introduction to Virtual Memory: Paging and Segmentation
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01 Oct (Fri) {lecture#SDR-09} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_cache8_vm1_01oct21.mp4,
lecture_notes_cache8_vm1_01oct21.pdf
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Paging and Segmentation (contd).
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05 Oct (Tue) {lecture#SDR-10} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_vm2_05oct21.mp4, lecture_notes_vm2_05oct21.pdf
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Paging and Segmentation (contd).
A little follow-up on RISC pipelining: overcoming hazards through
static scheduling, to alleviate cases of data hazards and control
hazards.
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06 Oct (Wed) {lecture#SDR-11} 10:00am-11:00am
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SDR
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MS-Teams folder:
video_vm3_06oct21.mp4, lecture_notes_vm3_06oct21.pdf
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Minor-2
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12 Oct (Tue) 05:00pm-06:00pm. Upload
deadline on gradescope: 06:30pm.
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SDR
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[Paper-and-pen exam, as described in the relevant email]
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