Instructor: Dr. Smruti R. Sarangi
TA: Prathmesh Kallurkar

Objective of the course: Design a 2 issue out-of-order pipeline in Verilog/VHDL for the SimpleRisc instruction set. It should have most of the basic features of modern
OOO designs including: branch prediction, renaming, wakeup-select, bypass, and precise exceptions.

Checkpoints:

1) Minor 1:
    a) Bimodal branch predictor
    b) Fetch and Decode
    c) Renaming, dependency checks, free list (or ROB based renaming)
    d) Pipeline these stages

2) Minor 2:
    a) Instruction Window
    b) Broadcast and Wakeup
    c) Execute and bypass
    d) A basic branchless code should be executing correctly at this stage
    e) Regsiter read/write

3) Major: 
    a) LSQ
    b) ROB and commit
    c) Branch misprediction and recovery
    d) Execution of large codes with loops