CURRICULUM VITAE

Personal Profile

Name		: Soumyadeb Mitra
Email Address		: smitra@cse.iitd.ac.in
Homepage		: http://www.cse.iitd.ernet.in/~ csd97407
Permanent Address		: C-804 M.S.Appartments K.G.Marg New Delhi-110001
Date of Birth		: April 10th 1980
Language Proficiency		: Hindi , English & Bengali

Academic Interests

• Computer Systems viz. Operating Systems , Distributed Systems
  
• Efficient implementations of Algorithms
  

Education

Course and Department	: 5th year , Dual Degree (BTech + MTech)
	Computer Science and Engineering
	Indian Institute of Technology , Delhi , India
C.G.P.A	: 9.09 / 10
Departmental Rank	: 1 of 18

Academic Awards

1. Recipient of CISCO Scholarship at IIT Delhi for pursuing graduate studies.
2. Secured 3rd rank in the Regional Mathematical Olympiad , Delhi Region.
3. Secured 11th rank in GATE Computer Science , an All India Examination for admission into graduate programs in Computer Science in India
4. Recipient of Institute Merit Award for securing 1st position in 20 students in fall & spring 1999.
5. Secured 1st rank in Predefined Software Design Contest in Tryst 99, anual technical festival of IITD.

Software and Hardware Skills and Experience

• Linux Kernel Internals
• Linux System Administration
• Language Skills : C, C++, Perl, Scheme, SML
• OS Familiarity :Linux, Unix, Windows
• S/W Tools/Libraries : OSkit, LEDA, Network Simulator, Lex, Yacc
• H/W tools used : Xilinx, VHDL, AHPL, VTune

Projects

• rtker - A Real Time Operating System (Major Project)
  
  Supervisor : Prof. S Banerjee, Prof. M Balakrishnan
  The aim of the project is to develop a Real Time Operating System for a multi-processor environment. We have developed a basic OS kernel(rtker) with support for threads, a minimal C library(printf/malloc), semaphores & real time interrupt handling. Some of the features of our OS are
  • Modular Design : We have tried to make rtker extremely modular. The architecture dependent code is clearly isolated from the architecture independent code.

    Plug-gable Scheduling : We have defined a new concept of a Scheduling API. rtker assumes that we have a scheduler object which has functions like sched_create_thread(), sched_heir_thread(). It calls these functions to schedule threads. Application developer can either chose from a predefined set of schedulers (like fifo,edf) or write these functions himself and thus optimize on algorithms and data structures used for scheduling. Two Stage Interrupt Handling : Since we intend to cater to the demands of a real time computing environment, rtker is completely preemptible. This leads to a two level handling of interrupts - the (fast)first half interrupt handling function where interrupts are disabled and a second half interrupt handling function which runs with a thread context. Support for Multiprocessors : rtker has been made multiprocessor safe. All the OS data structures are protected by spin locks. Since rtker is completely interruptible, we have defined protocols to prevent rtker from getting deadlocked because of these locks.

  At present rtker runs on x86 and Trimedia. We intend to port some real world vision applications to rtker to validate our design and implementation. In the next phase of the project, we would try to make the rtker run in a heterogeneous environment like UMS architecture from Cradle Inc. or in a homogeneous environment like x86-SMP.

• Framework for H/W - S/W partitioning in a RTOS (Spring 2001)
  
  Supervisor : Dr. S Banerjee, Dr. M Balakrishnan
  The purpose of this project was to extend an existing RTOS for supporting H/W - S/W partitioning of applications. The H/W platform we had was an FPGA board . We chose RTEMS as our base RTOS & ported the linux device driver for the FPGA board to RTEMS. We also ported the FPGA board programming library.

  Finally we had a OS interface which supported an application to be partitioned into hardware & software components , running of the hardware component on the FPGA board and the software on the processor. Communication mechanism between the FPGA & application was through either of polling, interrupt driven or DMA. We demonstrated the framework with an application for computing inner product of vectors, where the multiplication was carried out in hardware and the addition in software.

• External Memory Sorting using Parallel Disks (Summer 2000)
  
  Supervisor : Peter Sanders (MPII Germany)
  Sorting routines which make effective use of the speed up offered by a parallel disk architecture are surprisingly non trivial to design. Although MultiWay Mergesort is considered to be the standard algorithm for multi disk sorting , there are still a number of non-trivial issues like those involved with prefetching of buffers etc. We looked at this problem from two stand points firstly having a superior prefetching algorithm which reduces the number of total I/O's and having a better implementation which takes into consideration practical issues like I/O bus contention etc.

  We started with the algorithm proposed by Barve & Vitter. This algorithm had a drawback in requiring flushing of prefetched buffers. We had a better prefetching algorithm which did not require any flushing of buffers. It also made better use of I/O bus bandwidth since the I/O operations were asynchronous.
  We implemented & profiled the our algorithm on a SPARC-II machine with 6 disks.
  

• Range Search Algorithm in External Memory (Spring 2000)
  
  Supervisor : Dr. Sandeep Sen
  This project involved implementing an External Memory Triangular Range Search Algorithm. We modified the standard Ham-Sandwhich Cut Algorithm for handling huge data sets, much more than what can reside in the main memory. The modification of the standard algorithm led to an implementation which considerably reduced the number of I/O operation for a typical range search query. This substantially improved the query times.

• Software Estimation for Design of Embedded Systems (Fall 1999)
  Supervisor : Dr. M. Balakrishnan
  The aim of the project was to develop a methodology for selecting a processor, from a given set of processors, that is best suited for a particular application. The application was constrained by a deadline. The processor specification was in the form of number of FU's their delays, latencies & their interdependencies.

  We identified a number of parameters like number of arithmetic operations, number of floating point operations, number of Mac operations etc. which would characterize the application & extracted those parameters from it's intermediate representation. Next we estimated the inherit concurrency in the application by carrying out an ASAP schedule. This information along with the processor descriptions enabled us to reject processors that had redundant capability (like large number of ALU's) which the application could not harness.

  Finally we estimated the rough cycle count that application would require on a given processor by applying heuristic ideas. The cycle count enabled us to reject processors that were either too fast or too slow for the application to meet it's deadline.

  This project required extensive programming in C++ making use of the SUIF compiler system.
  
  
  

Projects done as a part of course work

• Design of an OS
  As part of the Operating Systems course, the project involved the design & implementation of an Operating System kernel. The kernel had the following features
  • Support For timesliced preemptive scheduling of threads
  • Semaphores for thread synchronization.
  • A complete thread/semaphore library
  Coding was done in C & Assembly
• Compiler Design
  This assignment involved writing a complete compiler for a Pascal like language. The language had Pascal syntax but had only two data types -Integers & Lists(which were more like perl arrays). The parser was developed using ML-Yacc/ML-lex.
  Coding was in SML
• Implementation of a Network File System with Public Key Authentication
  The project involved developing a Network File System using RPC's. The authentication was Public Key based (in contrast to IP based authentication used in NFS). We also implemented some additional features like both Client & Server side caching of data.
  Coding was in C
• Design and simulation of a CPU for handling Big Number Arithmetic The project involved complete High Level Design(Data Path) of a modified MIPS processor with an enhanced instruction set for handling big number operations. We also developed a cycle accurate simulator for the processor
• Design and Implementation of A Content Addressable Memory
  The project involved resolving various issues related to the functioning of a content addressable memory and their subsequent realization on a FPGA demo board.The tool used was Xilinx.
• Hardware Bubble Sorter
  Design of a hardware bubble sorter in VHDL

System Administration

I am involved in the system administration of our departmental lab. The lab is the primary lab of our department , being used by about 200 users. The lab houses about 50 client machines in addition to NIS, NFS, Samba, Proxy, Mail & Web Servers. Half of the clients are diskless & remote boot with a Flash Rom whereas the other half have local kernels but mount their root over NFS. All the machines run Linux.

As an administrator I had written a number of scripts for a variety of tasks like automated installations & upgradation , printer accounting etc.

Courses Taken (Along with grades¹)

General

Compiler Design Principles (A) , Programming Languages (A-) , Computer Networks (A-) , Operating Systems (B) , Digital Image Processing (A) , Computer Vision (A) , Database Management Systems (A) , File Structures & Information Systems A(-).

Computer Architecture

Computer Architecture (A) , Advanced Computer Architecture (A) , Digital Electronics (A) , Introduction to Electronic Circuits (A) , Digital Hardware Design (A) , Micro Processors (A) , CAD for Digital Systems (A).

 Theory and Algorithms 

Analysis & Design of Algorithms (A-) , Theory of Computation (A) , Computational Geometry (A) , Data Structures (A-) , Introduction to Logic for Computer Science A(-).

 Mathematics

Discrete Structures (A) , Probability & Stochastic Processes (A) , Mathematics I - Real Analysis (B) , Mathematics II - Fourier Series, Complex Analysis, Vectors (A-) , Mathematical programming & Optimization Techniques (A) , Linear Algebra (A) , Topology & Functional Analysis (A).