| Topic |
Slides used in lectures |
Textbook chapters |
| Introduction |
intro.pdf |
|
| Assembly Instructions |
ch2_slides.pdf |
ch2.pdf, all sections except 2.15, 2.17, 2.18 |
| Computer Arithmetic |
multiply_divide.pdf,
negative_numbers.pdf,
floating_point.pdf
|
ch3.pdf, all sections except 3.6-3.8 |
| Processor Design |
chapter4_1.pdf,
chapter4_2.pdf,
chapter4_3.pdf,
RISC5-controlsignals.pdf
|
Chapter 4 (till 4.8) and Appendix A (A.7 and A.8), processor code implementation at berkeley-repo
|
| Mid-term revision |
x86-MIPS.png,
revision.pdf,
midterm_2025.pdf,
midterm_2025_student1.pdf,
midterm_2025_student2.pdf,
midterm_2025_student3.pdf
minor2_2023.pdf
minor2_2023_student1.pdf,
minor2_2023_student2.pdf,
minor2_2023_student3.pdf,
|
|
Exceptions,
Out-of-order execution,
CPU extensions (superscalar,VLIW,SIMD) |
exceptions.pdf
out_of_order_execution.pdf
|
1. Orgainzation book 4.9 and 4.10
2. harris_harris_book.pdf for additional information on exceptions (Section 7.7), Superscalar processor (Section 7.8.3), Out of order processor (Section 7.8.4), Register renaming (Section 7.8.5), SIMD (Section 7.8.6)
3. quantitative_approach_book_ooo.pdf for out of order and Tomasulo's algorithm details (dynamic scheduling is another name for out of order execution).
|
| Memory Hierarchy |
cache-basics.pdf,
cache-friendly-programming.pdf,
pagetable_tlb.pdf,
pagetable_notes.pdf,
cache-coherence.pdf,
coherence_protocols.pdf,
false-sharing.pdf,
sram-dram.pdf
|
sarangi_memory_system.pdf (except inverted page table),
cache_coherence.pdf
|
| Major revision |
falsesharing.pdf,
practice.pdf,
major_2025.pdf,
major_2025_student1.pdf,
major_2025_student2.pdf,
major_2025_student3.pdf
major_2023.pdf
major_2023_student1.pdf,
major_2023_student2.pdf,
major_2023_student3.pdf,
|
|
