Evaluation plan: Assignments 40%, Mid-term 25%, End-term 35%
Attendance: fixed seats will be allotted after Jan 15, 2025, after which regular attendance will be taken. Sign attendance sheet everyday. Photos will be taken for TA checking against the signatures. Any case of wrong-doing will lead to F grade.
Attendance policy: standard. Less than 75% attendance means one grade less finally. No NP grade for audit students.
Audit pass criteria: 20 out of 40 in assignmnets. 30 out of 60 in exams. 75% attendance.
Piazza link: col216. Access code is col216 in small letters.
| TA name | Contact |
|---|---|
| Tejas Anand | Tejas.Anand.cs521@cse.iitd.ac.in |
| Eshan Jain | cs5200424@cse.iitd.ac.in |
| Si Siddhanth Raja | cs5200443@cse.iitd.ac.in |
| Abhishek Kumar | csy237587@cse.iitd.ac.in |
| Sarvesh Thakur | csz238547@cse.iitd.ac.in |
| S U Swakath | mcs232475@cse.iitd.ac.in |
| Topic | Slides used in lectures | Textbook chapters |
| Introduction, Performance Metrics | chapter1.pdf | Organization book Chapter 1 |
| Instruction Set Architecture | chapter2_1.pdf chapter2_2.pdf | Organization book Chapter 2, except 2.11 and Advanced Material |
| Computer Arithmetic | chapter3_1.pdf chapter3_2.pdf chapter3_3.pdf | Organization book Chapter 3 (till 3.4) and Appendix A (till A.6, without A.4) |
| Processor Design | chapter4_1.pdf chapter4_2.pdf chapter4_3.pdf RISC5-controlsignals.pdf | Organization book Chapter 4 (till 4.8) and Appendix A (A.7 and A.8), processor code implementation at berkeley-repo Practice problems revision1.pdf, revision2.pdf, loop-code-pipeline.pdf, 2023_minor2question.pdf |
| Memory Hierarchy | cache_organization.pdf cache_datastructures.pdf cache_coherence_MESI.pdf parallel_performance_falsesharing.pdf memory_hierarchy.pdf DRAM_disk_interface.pdf | Organization book Chapter 5, Quantitaive Approach book Chapters 5.1-5.3 on cache coherence |
| Floating point | fp_representation.pdf fp_arithmetic.pdf | Organization book Chapters 3.5 |
| Exceptions, Out-of-order execution, CPU extensions (superscalar,VLIW,SIMD) |
exceptions.pdf out_of_order_execution.pdf cpu_extensions.pdf |
1. Orgainzation book 4.9 and 4.10 2. harris_harris_book.pdf for additional information on exceptions (Section 7.7), Superscalar processor (Section 7.8.3), Out of order processor (Section 7.8.4), Register renaming (Section 7.8.5), SIMD (Section 7.8.6) 3. quantitative_approach_book_ooo.pdf for out of order and Tomasulo's algorithm details (dynamic scheduling is another name for out of order execution). |
| Practice problems for major | falsesharing1.pdf majorpaper_2023.pdf apr29class.pdf | Chapter 6 in Computer Systems book (especially 6.2-6.5). Solve the exercises. |