Evaluation plan: Assignments 40%, Minor1 15%, Minor2 15%, Major 30%
Piazza link: col216. Access code is the classroom where the classes are held in small letters.
| TA name | Contact |
|---|---|
| Sayam Sethi | cs1190399@cse.iitd.ac.in |
| Aman Gupta | Aman.Gupta.cs119@cse.iitd.ac.in |
| Chirag Mohapatra | cs5180403@cse.iitd.ac.in |
| Gundapu Nitheesh | jcs212239@csia.iitd.ac.in |
| Roomman Israili | jcs212243@csia.iitd.ac.in |
| Sarang Liladhar Drugkar | jcs212244@csia.iitd.ac.in |
| Suraj Kiran Mate | jcs212387@csia.iitd.ac.in |
| Devesh Kumar | mcs212130@cse.iitd.ac.in |
| Divy Baid | mcs212131@cse.iitd.ac.in |
| Topic | Supplementary Notes | Book Chapters | |
| Introduction, Performance Metrics | chapter1.pdf | Organization book, Chapter 1 | |
| Instruction Set Architecture | chapter2_1.pdf chapter2_2.pdf | Organization book Chapter 2 and Appendix A | |
| Computer Arithmetic | chapter3_1.pdf mult-div-tracing.pdf chapter3_2.pdf chapter3_3.pdf | Organization book Chapter 3 and Appendix A | |
| Processor Design | appendixb_1.pdf chapter4_1.pdf chapter4_2.pdf chapter4_3.pdf loop-code-pipeline.pdf pipeline-design-analysis.pdf | Organization book Chapter 4 and Appendix B | |
| Memory Hierarchy |
Slides: memoryhierarchy.pdf
cacheorganization.pdf
pagetable_tlb.pdf
cachecoherence1.pdf
cachecoherence2.pdf
Videos: DRAM vs. SRAM 1 bit SRAM 1 bit DRAM quiz, on why trenchcell is used in DRAM 1 bit memory to whole memory memory refresh quiz memory refresh quiz solution how to write to DRAM? Notes and revision problems: revision1.pdf revision2.pdf how arrays are laid out in memory looping patterns for spatial locality (check the loop examples and practice problems in 6.2, 6.5 and 6.6) |
Organization book Chapter 5, Quantitaive Approach book Chapters 5.1-5.3 on cache coherence | |
| Extra Topics on Security (not in exams) | Cache flush and reload attack in Usenix Security 2014 conference: paper, slides, code |