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Current PhD Students
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| Sakshi Tiwari |
| Ayushi Agarwal |
| Garima Modi |
| Naman Jain |
| Dinesh Joshi |
| Sohail Khan |
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MS (by Research)
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| Abhishek Kumar |
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Graduated PhD Students
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| Aritra Bagchi (2025. Post-doc at NUS.) |
| Divya Praneetha Ravipati (2024. Joined Intel.) |
| Shailja Pandey (2024. Joined Intel.) |
| Lokesh Siddhu (2022. Faculty member at IIT Guwahati) |
| Neetu Jindal (2019. Joined Intel. Jointly supervised by S. R. Sarangi.) |
| Sandeep Chandran (2018. Faculty member at IIT Palakkad. Jointly supervised by S. R. Sarangi.) |
| Rahul Jain (2017. Joined Reniac.) |
| Prasenjit Chakraborty (2015. Joined Intel.) |
| Namita Sharma (2015. Joined Intel.) |
| Vaibhav Jain (2015. Faculty member at DAVV. Jointly supervised by Anshul Kumar.) |
| Krishnaiah Gummidipudi (2013. Joined Intel. Jointly supervised by Anshul Kumar.) |
| B. V. N. Silpa (2012. Joined Nvidia.) |
| Neeraj Goel (2012. Faculty member at IIT Ropar. Jointly supervised by Anshul Kumar.) |
| Anant Vishnoi (2010. Joined Cadence. Jointly supervised by M. Balakrishnan.) |
| Aryabartta Sahu (2010. Faculty member at IIT Guwahati. Jointly supervised by M. Balakrishnan.) |
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Post-docs
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| Aritra Bagchi (2025. Post-doc at NUS.) |
| Dharamjeet (2023. Joined Intel.) |
| Rajesh Kedia (2022. Faculty member at IIT Hyderabad) |
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| Research |
Shared Cache Management
Collaborator: Intel, IBM, NXP, and Semiconductor Research Corporation (SRC)
The shared cache levels of the memory hierarchy present many opportunities in modern Multiprocessor Systems-on-Chip (MPSoCs) for intelligent control and management. Research problems we have studied in this space include: machine learning techniques to perform intelligent runtime adaptation, last level cache (LLC) bandwidth partitioning, LLC request vs. response arbitration, cache forwarding/bypassing, and co-optimising performance and endurance of non-volatile caches.
Project website for Machine Learned Machines including experimental platform software.
3D Stacked Systems and Thermal Management
3D stacking offers exciting new possibilities for compact, high-performance designs with high data access throughput, and performance-thermal trade-offs. We have studied Dynamic Thermal Management strategies co-ordinated with voltage/frequency scaling, task/data mapping decisions, and Neural Network-specific analysis, to deliver the highest performance in the presence of thermal constraints.
Emerging Technologies: CPU and Memory Energy/Performance/Thermal Modeling
Collaborator: NXP Semiconductors
We have spent considerable effort in the performance and energy modeling of CPU and Memory in a range of emerging technologies and conditions: 3D and 2.5D Stacked, FinFET, NC-FinFET, and Cryogenic systems.
Hardware Architectures for AI/Machine Learning
Collaborator: R Systems Centre of Excellence, Cadence
The popularity of AI/ML applications has led to various hardware architectures targeting their efficient execution. Hardware ML accelerators lead to several novel research problems related to the co-optimisation of the CPUs along with the accelerators. We are investigating architectural schemes for efficient ML computation and their interaction with system resources.
Memory/Data Organisation and Energy Efficiency
Collaborators: IBM, IMEC
In earlier work, we introduced the concept of Scratch Pad Memory (SPM) (P. R. Panda, N. D. Dutt, A. Nicolau, Efficient utilization of scratch-pad memory in embedded processor applications. ED&TC 1997) and investigated ways to partition on-chip data memory space between scratch pad memory and data cache. The book Memory issues in Embedded Systems-on-chip captures some of the recent developments on data memory optimisations in embedded systems. Our paper Data and memory optimization techniques for embedded systems (ACM TODAES, Apr 2001) has been the most downloaded paper of the journal for several years. Our book Power-efficient System Design surveys power-efficiency and energy-efficiency at different abstraction levels in computing systems.
Other Research Topics
- Power-efficiency in Graphics Processors
- Accelerating NoC Emulation
- High-level Synthesis
- Post-silicon Validation
Supported by:
- Cadence Design Systems
- Calypto Design Systems
- Freescale Semiconductor
- IBM
- Intel
- NXP Semiconductors
- Qualcomm
- R Systems Centre of Excellence
- Samsung
- Semiconductor Research Corporation
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