Publications

External Links: Google Scholar, DBLP

Books

Book Cover: Power-efficient System Design Power-efficient System Design
Preeti Ranjan Panda, Aviral Shrivastava, B. V. N. Silpa, Krishnaiah Gummidipudi
Springer, New York, 2010. 		Book Cover: Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
Kluwer Academic Publishers, Norwell, 1999.

Book Chapters

  1. Manycore processor architectures Prasenjit Chakraborty, Bharath Narasimha Swamy, and Preeti Ranjan Panda, Many-Core Computing -- Hardware and Software, Eds. Bashir M. Al-Hashimi and Geoff V. Merrett, IET 2019.
  2. Debug Data Reduction Techniques, Sandeep Chandran and Preeti Ranjan Panda, Post-silicon Validation and Debug, Eds. Prabhat Mishra and Farimah Farahmandi, Springer 2018.
  3. Memory Architectures, Preeti Ranjan Panda, in Handbook of Hardware/Software Codesign, Eds. Soonhoi Ha and Juergen Teich, Springer, 2017
  4. Energy-efficient Memory Port Assignment, Preeti Ranjan Panda and Lakshmikantam Chitturi, in Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach, Eds. Florin Balasa and Dhiraj Pradhan, Chapman & Hall/CRC Press, 2011
  5. Power Optimisation Strategies Targeting the Memory Subsystem, Preeti Ranjan Panda, in Designing Embedded Processors - A Low Power Perspective (eds. Jorg Henkel and Sri Parameswaran), Springer, pp131-155, 2007
  6. Memory Architectures for Embedded Systems-on-Chip, Preeti Ranjan Panda and Nikil Dutt, Lecture Notes in Computer Science (LNCS) Vol. 2552, Springer-Verlag, 2002, pp. 647-662
  7. Improving Cache Performance through Tiling and Data Alignment, Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau, Lecture Notes in Computer Science (LNCS) Vol. 1253, Springer-Verlag, 1997, pp. 167-185

Journal Papers

  1. G Modi, P Singla, N Jindal, A Mandal, P Panda: FARRE: Fairness Aware Request Response Arbitration in Shared Caches, ACM Trans. Embed. Comput. Syst. (TECS), 24 (5s) (2025)
  2. D Joshi, A Bagchi, PR Panda: SHARP: SHARing-Aware Cache Writeback byPass, ACM Trans. Embed. Comput. Syst. (TECS), 24 (5s) (2025)
  3. Divya Praneetha Ravipati, Victor M. van Santen, Shivendra Singh Parihar, Yogesh Singh Chauhan, Preeti Ranjan Panda, Hussam Amrouch: Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling Down to 10K in Advanced 7nm FinFETs. IEEE Trans. Computers (TOC) 74(8): 2567-2580 (2025)
  4. Ayushi Agarwal, Pulkit Goel, P. J. Joseph, Prokash Ghosh, Sourav Roy, Preeti Ranjan Panda: FLASH: Deadline-Aware Flexible LLC Arbitration and Scheduling for Hardware Accelerators. ACM Trans. Embed. Comput. Syst. (TECS) 24(6): 165:1-165:34 (2025)
  5. Divya Praneetha Ravipati, Ramanuj Goel, Victor M. van Santen, Hussam Amrouch, Preeti Ranjan Panda: CAPE: Criticality-Aware Performance and Energy Optimization Policy for NCFET-Based Caches. IEEE Trans. Computers (TOC) 73(12): 2830-2843 (2024)
  6. Shailja Pandey, Sayam Sethi, Preeti Ranjan Panda: 3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD) 43(8): 2263-2276 (2024)
  7. Aritra Bagchi, Ohm Rishabh, Preeti Ranjan Panda: NOVELLA: Nonvolatile Last-Level Cache Bypass for Optimizing Off-Chip Memory Energy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD) 43(11): 3913-3924 (2024)
  8. Aritra Bagchi, Dinesh Joshi, Preeti Ranjan Panda: COBRRA: COntention-aware cache Bypass with Request-Response Arbitration. ACM Trans. Embed. Comput. Syst. 23(1): 12:1-12:30 (2024)
  9. Shailja Pandey, Preeti Ranjan Panda: NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN Performance. ACM Trans. Embed. Comput. Syst. (TECS) 23(6): 96:1-96:30 (2024)
  10. Shailja Pandey, Lokesh Siddhu, Preeti Ranjan Panda: NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching. ACM Trans. Design Autom. Electr. Syst. (TODAES) 29(1): 19:1-19:35 (2024)
  11. Aritra Bagchi, Dharamjeet, Ohm Rishabh, Manan Suri, Preeti Ranjan Panda: POEM: Performance Optimization and Endurance Management for Non-volatile Caches. ACM Trans. Design Autom. Electr. Syst. (TODAES) 29(5): 1-36 (2024)
  12. Aritra Bagchi, Dinesh Joshi, Preeti Ranjan Panda: COBRRA: COntention aware cache Bypass with Request-Response Arbitration. ACM Trans. Embed. Comput. Syst. (TECS) 23(1), 1-30 (2024)
  13. Shailja Pandey, Lokesh Siddhu, Preeti Ranjan Panda: NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching. ACM Transactions on Design Automation of Electronic Systems (TODAES), 29(1), 1-35 (2023)
  14. Garima Modi, Aritra Bagchi, Neetu Jindal, Ayan Mandal, Preeti Ranjan Panda: CABARRE: Request Response Arbitration for Shared Cache Management. ACM Trans. Embed. Comput. Syst. (TECS) 22(5s): 130:1-130:24 (2023)
  15. Lokesh Siddhu, Aritra Bagchi, Rajesh Kedia, Isaar Ahmad, Shailja Pandey, Preeti Ranjan Panda: Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure. ACM Trans. Embed. Comput. Syst. (TECS) 22(6): 104:1-104:27 (2023)
  16. Divya Praneetha Ravipati, Victor M. van Santen, Sami Salamin, Hussam Amrouch, Preeti Ranjan Panda: Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT. IEEE Trans. Very Large Scale Integr. Syst. (TVLSI) 31(9): 1280-1293 (2023)
  17. Shailja Pandey, Preeti Ranjan Panda: NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (TCAD) 41(11): 3602-3613 (2022)
  18. Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, J rg Henkel, Preeti Ranjan Panda: CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. ACM Trans. Archit. Code Optim. (TACO) 19(3): 44:1-44:25 (2022)
  19. Divya Praneetha Ravipati, Rajesh Kedia, Victor M. van Santen, J rg Henkel, Preeti Ranjan Panda, Hussam Amrouch: FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies. IEEE Trans. Very Large Scale Integr. Syst. (TVLSI) 30(3): 339-352 (2022)
  20. Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda: Leakage-Aware Dynamic Thermal Management of 3D Memories. ACM Trans. Design Autom. Electr. Syst. (TODAES) 26(2): 12:1-12:31 (2021)
  21. Hadi Brais, Rajshekar Kalayappan, and Preeti Ranjan Panda, A Survey of Cache Simulators, ACM Computing Surveys (CSUR), Feb 2021
  22. Neetu Jindal, Shubhani Gupta, Divya Praneetha Ravipati, Preeti Ranjan Panda, and Smruti R. Sarangi, Enhancing Network-on-Chip Performance by Reusing Trace Buffers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 39(4), 922-935 (2020)
  23. Sakshi Tiwari, Shreshth Tuli, Isaar Ahmad, Ayushi Agarwal, and Preeti Ranjan Panda, REAL: REquest Arbitration in Last Level Caches, ACM Transactions on Embedded Computing Systems (TECS), 18(6): 115:1-115:24 (2020)
  24. Hadi Brais and Preeti Ranjan Panda, Alleria: An Advanced Memory Access Profiling Framework, ACM Transactions on Embedded Computing Systems (TECS), 18(5s): 81:1-81:22 (2019)
  25. Lokesh Siddhu and Preeti Ranjan Panda, PredictNcool: Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor, ACM Transactions on Embedded Computing Systems (TECS), 18(5s): 64:1-64:22 (2019)
  26. Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi: Reusing Trace Buffers as Victim Caches. IEEE Trans. VLSI Syst. (TVLSI) 26(9): 1699-1712 (2018)
  27. Rahul Jain, Preeti Ranjan Panda, and Sreenivas Subramoney, Cooperative Multi-Agent Reinforcement Learning based Co-optimization of Cores, Caches, and On-chip Network, ACM Transactions on Architecture and Code Optimization (TACO), 14(4):32:1-32:25, 2017.
  28. Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharyya, Deepak Chauhan, Sharad Kumar: Managing Trace Summaries to Minimize Stalls During Postsilicon Validation. IEEE Trans. VLSI Syst. (TVLSI) 25(6): 1881-1894 (2017)
  29. Prasenjit Chakraborty, Preeti Ranjan Panda, Sandeep Sen, Partitioning and Data Mapping in Reconfigurable Cache and Scratch Pad Memory based Architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), 22(1), 2016
  30. Iason Filippopoulos, Namita Sharma, Per Gunnar Kjeldsberg, Francky Catthoor, Preeti Ranjan Panda, Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures , ACM Transactions on Embedded Computing Systems (TECS), 15(3), 2016
  31. Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Min Li, Prashant Agrawal, Data Flow Transformation for Energy Efficient Implementation of Givens Rotation Based QRD , ACM Transactions on Embedded Computing Systems (TECS), 15(1), 2016
  32. Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda, Area-Aware Cache Update Trackers for Postsilicon Validation , IEEE Transactions on VLSI Systems(TVLSI), 24(5), 2016
  33. Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Praveen Raghavan, Tom Vander Aa, Array Interleaving - An Energy-Efficient Data Layout Transformation , ACM Transactions on Design Automation of Electronic Systems (TODAES), 20(3), 2015
  34. Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda, Shared-port register file architecture for low-energy VLIW processors , ACM Transactions on Architecture and Code Optimization (TACO) 11(1): 1 (2014)
  35. Exploiting UML based validation for compliance checking of TLM 2 based models, Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda, Design Autom. for Emb. Sys. (DAES) 16(2): 93-113 (2012)
  36. Compressing Cache State for Post-Silicon Processor Debug, Preeti Ranjan Panda, M. Balakrishnan, and Anant Vishnoi, IEEE Transactions on Computers (TC), 60(4): 484-497, 2011
  37. Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures, Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, and Anshul Kumar , International Journal of Parallel Programming (IJPP), Vol. 35, No. 6, pp507-527, 2007
  38. Memory Allocation and Mapping in High-level Synthesis: An Integrated Approach, Jaewon Seo, Taewhan Kim, and Preeti Ranjan Panda , IEEE Transactions on VLSI Systems (TVLSI), Vol. 11, No. 5, October 2003
  39. Data Memory Organization and Optimizations in Application-Specific Systems, P. R. Panda, N. D. Dutt, A. Nicolau, F. Catthoor, A. Vandecappelle, E. Brockmeyer, C. Kulkarni, and E. de Greef , IEEE Design and Test of Computers (D & T), Vol. 18, No. 3, May/June 2001.
  40. Data and memory optimization techniques for embedded systems, P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, and P. G. Kjeldsberg, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 6, No. 2, April 2001 (Most Downloaded ACM TODAES Paper)
  41. On chip vs. off chip memory: the data partitioning problem in embedded processor-based systems , Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau , ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 5, No. 3, July 2000 (Listed in Top 10 Downloaded ACM TODAES Papers)
  42. Low Power Memory Mapping through Reducing Address Bus Activity, Preeti Ranjan Panda and Nikil D. Dutt , IEEE Transactions on VLSI Systems (TVLSI), Vol. 7, No. 3, September 1999
  43. High-Level Synthesis with SDRAMs and RAMBUS DRAMs , Asheesh Khare, Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau , IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Vol. E82A, No. 11, pp 2347-2355, 1999
  44. Augmenting Loop Tiling with Data Alignment for Improved Cache Performance , Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau , IEEE Transactions on Computers (TC), Vol 48, No. 2, February 1999
  45. Local Memory Exploration and Optimization in Embedded Systems , Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 18, No. 1, January 1999.
  46. Incorporating DRAM Access Modes in High-Level Synthesis , Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 17, No. 2, February 1998
  47. Memory Data Organization for Improved Cache Performance in Embedded Processor Applications , Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau , ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 2, No. 4, October 1997
  48. Estimating the complexity of synthesized designs from FSM Specifications , Biswadip Mitra, Preeti Ranjan Panda, and P. Pal Chaudhary, IEEE Design & Test of Computers (D & T) , March 1993

Conference Papers

  1. Ayushi Agarwal, Radhika Dharwadkar, Isaar Ahmad, Krishna Kumar, P. J. Joseph, Sourav Roy, Prokash Ghosh, Preeti Ranjan Panda: APPAMM: Memory Management for IPsec Application on Heterogeneous SoCs. ( VLSI-SoC), 2024 (Best Paper Candidate)
  2. Shailja Pandey, Preeti Ranjan Panda: NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth Memory. ( ESWEEK/CODES+ISSS ) 2022 (Best Paper Candidate)
  3. Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda: CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance. ( DATE) 2022: 1377-1382 (Best Paper Candidate)
  4. Neetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, Shikhar Tuli: DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring. Design Automation Conference (DAC), Las Vegas, 2019: 99
  5. Lokesh Siddhu, Preeti Ranjan Panda: FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories. Design Automation and Test in Europe (DATE), 2019: 272-275
  6. Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf K hnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra: Techniques for Debug of Low Power SoCs. 20th International Workshop on Microprocessor/SoC Test, Security and Verification (MTV) 2019: 45-49
  7. Vivek Kamalkant Parmar, Swatilekha Majumdar, Preeti Ranjan Panda, Manan Suri: Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN Applications. Intl. Conference in VLSI Design and Embedded Systems (VLSI Design): 281-286, New Delhi, 2019
  8. Preeti Ranjan Panda, Namita Sharma, Srikanth Kurra, Khushboo Anil Bhartia, Neeraj Kumar Singh: Exploration of Loop Unroll Factors in High Level Synthesis. Intl. Conference in VLSI Design and Embedded Systems (VLSI Design), Pune, January 2018
  9. Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi: Reusing trace buffers to enhance cache performance. Design Automation and Test in Europe (DATE), Lausanne, 2017: 572-577
  10. Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney: A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. Design Automation and Test in Europe (DATE), Lausanne, 2017: 800-80
  11. R. Jain, P. R. Panda, and S. Subramoney, Machine Learned Machines: Adaptive Co-optimization of Caches, Cores, and On-chip Network, Design Automation and Test in Europe (DATE), Dresden, March 2016 (Best Interactive Presentation Candidate)
  12. S. Chandran, P. R. Panda, S. R. Sarangi, D. Chauhan, and S. Kumar, Extending Trace History Through Tapered Summaries in Post-silicon Validation , Asia and South Pacific Design Automation Conference (ASP-DAC), Macau, January 2016 (Best Paper Candidate)
  13. S. Chandran, E. Peter, P. R. Panda, S. R. Sarangi, A Generic Implementation of Barriers using Optical Interconnects, Intl. Conference in VLSI Design and Embedded Systems (VLSI Design), Kolkata, January 2016
  14. Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Energy efficient FFT implementation through stage skipping and merging, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Amsterdam, October 2015
  15. Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma, Vaidyanathan Srinivasan, Dipankar Sarma, Power Optimization Techniques for DDR3 SDRAM , Intl. Conference in VLSI Design and Embedded Systems (VLSI Design), Bangalore, January 2015: 310-315
  16. Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan, Array scalarization in high level synthesis, Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, January 2014: 622-627
  17. Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan, Energy optimization in Android applications through wakelock placement , Design Automation and Test in Europe (DATE), 2014
  18. Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor, Energy efficient data flow transformation for Givens Rotation based QR Decomposition ,Design Automation and Test in Europe (DATE), 2014
  19. Preeti Ranjan Panda, Sourav Roy, Srikanth Chandrasekaran, Namita Sharma, Jasleen Kaur, Sarath Kumar Kandalam, Nagaraj N., High level energy modeling of controller logic in data caches , ACM Great Lakes Symposium on VLSI (GLS-VLSI), 2014, 45-50
  20. Prasenjit Chakraborty, Preeti Ranjan Panda, SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems , International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2013
  21. Namita Sharma, Tom Vander Aa, Prashant Agrawal, Praveen Raghavan, Preeti Ranjan Panda, and Francky Catthoor, Data memory optimizations in LTE downlink ,International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2013
  22. Space sensitive cache dumping for post-silicon validation
    Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda
    Design, Automation and Test in Europe (DATE'13) 2013: 497-502
  23. Power Supply Efficiency Aware Server Allocation in Data Centers
    Preeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan
    Intl. Conference on VLSI Design and Embedded Systems (VLSI Design'13), Pune, 2013: 233-238
  24. Integrating software caches with scratch pad memory
    Prasenjit Chakraborty, Preeti Ranjan Panda
    15th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'12) 2012, Tampere, Finland, pp 201-210
  25. Efficient on-line algorithm for maintaining k-cover of sparse bit-strings
    Amit Kumar, Preeti Ranjan Panda, Smruti R. Sarangi
    IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science (FSTTCS'12), Hyderabad, 2012, pp 249-256
  26. Exploiting temporal decoupling to accelerate trace-driven NoC emulation
    Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar
    9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'11), Taipei, Taiwan, 2011, pp 315-324
  27. A SysML Profile for Development and Early Validation of TLM 2.0 Models
    Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
    7th European Conference Modelling Foundations and Applications (ECMFA'11), Birmingham, UK, 2011, pp 299-311
  28. A UML based framework for efficient validation of TLM 2 models
    Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
    Forum on Specification & Design Languages, (FDL'11), Oldenburg, Germany, 2011, pp 1-8
  29. Enhancing post-silicon processor debug with incremental cache state dumping
    Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan
    18th IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC'10), Madrid, Spain, 27-29 September 2010, pp 55-60
  30. Front-End Design Flows for Systems on Chip: An Embedded Tutorial
    Anshul Kumar, Preeti Ranjan Panda
    Intl. Conference on VLSI Design and Embedded Systems (VLSI Design'10), pp 417-422
  31. FastFwd: An Efficient Hardware Acceleration Technique for Trace-driven Network-on-Chip Simulation
    Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, and Anshul Kumar
    (CODES+ISSS'10), Scottsdale, USA, October 2010
  32. Rank Based Dynamic Voltage and Frequency Scaling for Tiled Graphics Processors
    B. V. N. Silpa, Gummidipudi Krishnaiah, and Preeti Ranjan Panda
    (CODES+ISSS'10), Scottsdale, USA, October 2010 (Best Paper Candidate)
  33. Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine
    B. V. N. Silpa, Kumar S. S. Vemuri, and Preeti Ranjan Panda
    International Symposium on Visual Computing (ISVC'09 (1))(LNCS 5785), Las Vegas, USA, November 2009, pp 111-124
  34. Online Cache State Dumping for Processor Debug
    A. Vishnoi, Preeti Ranjan Panda, and M. Balakrishnan
    Design Automation Conference (DAC'09), San Francisco, USA, July 2009
  35. Cache Aware Compression for Processor Debug Support
    A. Vishnoi, Preeti Ranjan Panda, and M. Balakrishnan
    Design, Automation and Test in Europe (DATE'09), Nice, France, April 2009
  36. A Generic Platform for Estimation of Multi-threaded Program Performance on Heterogeneous Multiprocessor
    A. Sahu, M. Balakrishnan, and Preeti Ranjan Panda
    Design, Automation and Test in Europe (DATE'09), Nice, France, April 2009
  37. Texture Filter Memory: A Power-efficient and Scalable Texture Memory Architecture for Mobile Graphics Processors
    B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, and G. S. Visweswaran
    IEEE/ACM International Conference on Computer Aided Design (ICCAD '08), San Jose, November 2008
  38. Unified Modeling Abstraction for Fast Simulation and Emulation
    G. Krishnaiah, Preeti Ranjan Panda, Ashok Janannathan, Sreenivas Subramoney, and Anshul Kumar
    3rd Workshop on Architectural Research Prototyping (WARP'08), Beijing, China, June 2008
  39. REWIRED - Register Write Inhibition by Resource Dedication
    Pushkar Tripathi, Rohan Jain, Srikanth Kurra, and Preeti Ranjan Panda
    13th Asia and South Pacific Design Automation Conference (ASPDAC '08), Seoul, Korea, pp28-31, January 2008
  40. An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform
    Rahul Jain and Preeti Ranjan Panda
    Intl. Symposium on Circuits and Systems (ISCAS'07), New Orleans, May 2007
  41. The Impact of Loop Unrolling on Controller Delay in High Level Synthesis
    Srikanth Kurra, Neeraj K Singh and Preeti Ranjan Panda
    Design Automation and Test in Europe (DATE'07), Nice, France, April 2007
  42. Power Reduction in VLIW Processor with Compiler Driven Bypass Network
    Neeraj Goel, Anshul Kumar and Preeti Ranjan Panda
    Intl. Conference on VLSI Design and Embedded Systems (VLSI'07), Bangalore, Jan 2007
  43. Customization of Register File Banking Architecture for Low Power
    Rakesh Nalluri, Rohan Garg and Preeti Ranjan Panda
    Intl. Conference on VLSI Design and Embedded Systems (VLSI'07), Bangalore, Jan 2007
  44. Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
    Rahul Jain and Preeti Ranjan Panda
    Intl. Conference on VLSI Design and Embedded Systems (VLSI'07), Bangalore, Jan 2007
  45. Energy efficient application specific banked register files
    Rakesh Nalluri and Preeti Ranjan Panda
    10th IEEE VLSI Design and Test Symposium (VDAT '06), Goa, August 2006, pp56-65
  46. A power efficient architecture for 2-D Discrete Wavelet Transform
    Rahul Jain and Preeti Ranjan Panda
    10th IEEE VLSI Design and Test Symposium (VDAT '06), Goa, August 2006, pp121-129
  47. Rapid estimation of control delay from high-level specifications
    Gagan Raj Gupta, Madhur Gupta, and Preeti Ranjan Panda
    43rd Design Automation Conference (DAC '06), San Francisco, USA, July 2006, pp455-458
  48. Abridged Addressing: A Low Power Memory Addressing Strategy
    Preeti Ranjan Panda
    11th Asia and South Pacific Design Automation Conference (ASPDAC '06), Yokohama, Japan, January 2006, pp892-897
  49. A technique for predicting the effect of data cache associativity
    Viresh Kumar and Preeti Ranjan Panda
    9th IEEE VLSI Design and Test Symposium (VDAT '05), Bangalore, August 2005, pp259-268
  50. Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
    Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, and Anshul Kumar
    Design Automation and Test in Europe (DATE '05), Munich, March 2005, pp730-735
  51. Extracting Exact Finite State Machines from Behavioral SystemC Descriptions
    Vikram Singh Saun and Preeti Ranjan Panda
    18th International Conference on VLSI Design (VLSI Design '05), Kolkata, January 2005, pp280-285
  52. Memory Architectures for Embedded Systems-on-Chip (invited paper)
    Preeti Ranjan Panda and Nikil Dutt
    9th International Conference on High Performance Computing (HiPC 2002), December 2002
  53. An Energy-conscious Algorithm for Memory Port Allocation
    Preeti Ranjan Panda and Lakshmikantam Chitturi
    IEEE/ACM International Conference on Computer Aided Design  (ICCAD '02), San Jose, November 2002
  54. An Integrated Algorithm for Memory Allocation and Assignment in High-level Synthesis
    Jaewon Seo, Taewhan Kim, and Preeti Ranjan Panda
    39th Design Automation Conference (DAC '02), New Orleans, June 2002
  55. SystemC - A modeling platform supporting multiple design abstractions (invited paper)
    Preeti Ranjan Panda
    International Symposium on System Synthesis (ISSS '01), Montreal, October 2001
  56. Cache-efficient memory layout of aggregate data structures
    Preeti Ranjan Panda, Luc Semeria, and Giovanni de Micheli
    International Symposium on System Synthesis (ISSS '01), Montreal, October 2001
  57. Application Specific Memory Customization (invited paper)
    Preeti Ranjan Panda
    SSGRR International Conference on Advances in Computer Infrastructure, L'Aquila, Italy, July/August 2000
  58. Memory Bank Customization and Assignment in Behavioral Synthesis
    Preeti Ranjan Panda
    IEEE/ACM International Conference on Computer Aided Design  (ICCAD '99), San Jose, November 1999
  59. High-Level Synthesis with Synchronous and RAMBUS DRAMs
    Asheesh Khare, Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    The Eighth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'98), Sendai, Japan, October 1998
  60. Data Cache Sizing for Embedded Processor Applications
    Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    Design Automation and Test in Europe (DATE'98), Paris, February 1998, pp925-926
  61. Exploiting Off-Chip Memory Access Modes in High-Level Synthesis
    Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    IEEE/ACM International Conference on Computer Aided Design (ICCAD '97), San Jose, November 1997
  62. A Data Alignment Technique for Improving Cache Performance
    Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau
    International Conference on Computer Design (ICCD '97), Austin, October 1997
  63. Architectural Exploration and Optimization of Local Memory in Embedded Systems
    Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    International Symposium on System Synthesis (ISSS '97), Antwerp, September 1997
  64. Improving Cache Performance through Tiling and Data Alignment
    Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau
    The 4th International Symposium on Solving Irregularly Structured Problems in Parallel (IRREGULAR'97), Paderborn, June 1997
  65. Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications
    Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    European Design and Test Conference (ED & TC '97), Paris, March 1997
  66. Behavioral Array Mapping into Multiport Memories Targeting Low Power
    Preeti Ranjan Panda and Nikil D. Dutt
    10th International Conference on VLSI Design (VLSI Design '97), Hyderabad, January 1997
  67. Memory Organization for Improved Data Cache Performance in Embedded Processors
    Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    International Symposium on System Synthesis (ISSS '96), La Jolla, November 1996
  68. Low Power Mapping of Behavioral Arrays to Multiple Memories
    Preeti Ranjan Panda and Nikil D. Dutt
    International Symposium on Low Power Electronics and Design (ISLPED '96), Monterey, August 1996
  69. Reducing Address Bus Transitions for Low Power Memory Mapping
    Preeti Ranjan Panda and Nikil D. Dutt
    European Design and Test Conference (ED & TC '96), Paris, March 1996
  70. 1995 High Level Synthesis Design Repository
    Preeti Ranjan Panda and Nikil D. Dutt
    International Symposium on System Synthesis (ISSS '95), Cannes, September 1995
  71. Fibre Channel Protocol: Formal Specification and Verification
    Vijay Nagasamy, Sreeranga Rajan, and Preeti Ranjan Panda
    Silicon Valley Networking Conference (SVNC '95), San Jose, April 1995
  72. Estimating the complexity of synthesized designs from FSM Specifications
    Biswadip Mitra, Preeti Ranjan Panda, and P. Pal Chaudhary
    5th International Conference on VLSI Design (VLSI Design '92), Bangalore, Jan 1992 (Honourable Mention Award)
  73. A Flexible Scheme for State Assignment Based on Characteristics of the FSM
    Biswadip Mitra, Preeti Ranjan Panda, and P. Pal Chaudhary
    International Conference on Computer Aided Design (ICCAD '91), Santa Clara, November 1991
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