Sir,
This is my preference for the project


1. Project no. 11- Fonding optimal ----- DSP applications.
2. No. # Simulation of Queuing Model =-------------------- queue size.
3. no. cache coherence protocol no. 2.

regards
Lava Bhargava

Hi Arya,

Please find our choice of projects in decreasing order of priority:

1. Project no 1.     Cache coherence protocol simulation I(Berkley vs 
invalidate)
2. Project no 7     Simulation of diff. bus arbitration policy (assign3)
3. Project no 8     Implementation of multiple request generator in 
shared I&D cache (assign3).

Thanks,
Puneet 2004JVL2431
Rajiv  2004JVL2430

Sir

Kindly Allocate one of these two projects for our group.

12. Design of VLIW processor using BlockSim(Fetch Mechanism)
6      Loop Unrolling + PCA using ArchOpt tool (assign 2)

2005MCS2959 Kiran C
2005MCS2966 Ganesh VS

-- 
Kiran C
2005MCS2959
M.Tech Computer Science & Engineering - 2nd Semester
IIT Delhi

Sir

Kindly Allocate one of these two projects for our group.

12. Design of VLIW processor using BlockSim(Fetch Mechanism)
6      Loop Unrolling + PCA using ArchOpt tool (assign 2)

manish kothawade
Rajbhan Singh Bhadoria
Computer Science and Engineering
IIT Delhi

Hi Aryabartta,

My choices for the course project in decreasing order of preference are:

3     Implementation of multiple request generator in shared I&D cache
(assign3).

9     Integration of new cache simulator with dinero & cacti(assign 3).

1     Cache coherence protocol simulation I(Berkley vs invalidate)

Thanks,
Apurva

-----

Apurva Kumar,
Research Staff Member,
IBM India Research Lab
Phone: +91-11-51292143
Fax: +91-11-26861555

  
Our preferences (in order) for project are:

   7.) Simulation of different bus arbitration policy (assign 3)

   3.)Simulation of queuing model for finding queue size for p% rejection 

   11.)Finding optimal parameter of VLIW processor for DSP application

 Regards,
 
   Amarinder Singh Randhawa(2005MCS2957)
                  &
   Nitya Prakash(2005MCS2953)

My choices for the project are

Preference 1:
10  Instruction encoding in VLIW using VIES (vliw
instr encoding scheme)

Preference 2:
3 Simulation of Queuing Model for finding queue size
for p% rejection and finding  p% rejection for fixed
queue size.

Preference 3:
7 Simulation of diff. bus arbitration policy (assign3)


With regards
Awashesh_kumar
2005jvl2464
Rahul Nagarajan
2005jvl2467

Hello Sir,
          These are the preferences of our project in decreasing
preference order.

        Option 1:-  Proj No.11(Optimal design parameters of VLIW processor
for DSP applications.
         Option 2:- Proj No.9 (Integration of new cache simulator with
dinero &cacti)
        Option 3:- Proj No.6 (Loop Unrolling + PCA using Archopt tool)

        Option 4:-  Proj No.10 (Instruction Encoding in VLIW using VIES)

                                          Bye,
                                             K.Rakesh Kumar(2005JVL2463)
                                            Tushar Ajit Khadtare(2005JVL2476)

Hi,

My preference list is:

a)  2. Cache coherence protocol simulation II(Illinois vs Berkley)
b)  1. Cache coherence protocol simulation I(Berkley vs invalidate)
c)  8. Implementation of multiple request generator in shared I&D 
cache (assign3).

Thanks,
Rahul Malik
2002442
Group-1

Sir,

 List of preference for ALS Project
1.*Simulation of Queuing Model for finding queue size for p% rejection and
finding p% rejection for fixed queue size*
**
2.*Simulation intelligent multi-banking memory service *

3.*Multiprocessor interconnection protocol(Tree, MESH, Hypercube)*




reagrds
rajbahadur
2000129/csu00129