publications

(Please note that all of these papers are only preprints. For the published versions, please visit the website of the publisher. All the copyrights belong to the respective publishers.) 

Our list of patents can be found here.

2018

C51) Energy Efficient Scheduling in IoT Networks, Smruti R. Sarangi, Sakshi Goel and Bhumika Singh, ACM Symposium on Applied Computing (SAC), Pau, France (accepted)

C50) HPXA: A Highly Parallel XML Parser, Isaar Ahmad, Sanjog Patil, and Smruti R. Sarangi, DATE (Design Automation and Test in Europe), Dresden, Germany. (accepted)

2017

C49) Expander: Lock-Free Cache for a Concurrent Data Structure, Pooja Aggarwal, Smruti R. Sarangi, HiPC (High Performance Computing), Jaipur, India (pdf)

C48)  NUPLet: A Photonics Based Multi-Chip NUCA Architecture, Janibul Bashir, Smruti R. Sarangi, ICCD (International Conference on Computer Design), Boston, USA (pdf)

C47) SchedTask: A Hardware-Assisted Task Scheduler, Prathmesh Kallurkar, Smruti R. Sarangi, MICRO (International Symposium on Microarchitecture), Boston, USA (pdf)

C46) Poster: BigBus: A Scalable Optical Interconnect by Eldhose Peter, Janib-ul Bashir, and Smruti R. Sarangi. PACT (Parallel Architectures and Compilation Techniques), Portland, USA. proceedings paper: (pdf)

J18) ParSim: A Parallel Simulator for Multicore Processors by Geetika Malhotra, Rajshekar Kalayappan, Seep Goel, Pooja Aggarwal, Abhishek Sagar, and Smruti R. Sarangi. ACM Transactions on Modeling and Computer Simulation. (ACM TOMACS), Volume 27, Issue 3, Aug, 2017 (pdf)

J17) Managing Trace Summaries to Minimize Stalls During Post-Silicon Validation by Sandeep Chandran, Preeti Panda, Smruti R. Sarangi, Ayan Bhattacharya, Deepak Chauhan, Sharad Kumar, IEEE Transactions on VLSI (pdf)

J16) Optical Overlay NUCA: A High Speed Substrate for Shared L2 Caches, by Eldhose Peter, Anuj Arora, Janibul Bashir, Akriti Bagaria, and Smruti R. Sarangi. ACM Journal on Emerging Technologies in Computing Systems. (preprint)

J15) Internet of Things: Architectures, Protocols, and Applications by Pallavi Sethi, and Smruti R. Sarangi. Journal of Electrical and Computer Engineering. Volume 2017, DOI Link, (pdf)

C45) Reusing Trace Buffers to Enhance Cache Performance, Neetu Jindal, Preeti R. Panda, and Smruti R. Sarangi. DATE (Design Automation and Test in Europe), Lausanne, Switzerland. (pdf)

C44) A Hardware Implementation of the MCAS Synchronization Primitive, Sristhy Patel, Rajshekar Kalayappan, Ishani Mahajan, and Smruti R. Sarangi. DATE (Design Automation and Test in Europe), Lausanne, Switzerland. (pdf) (full paper + appendix)

C43) A Fast Leakage Aware Simulator for 3D Chips, Hameedah Sultan, and Smruti R. Sarangi, DATE (Design Automation and Test in Europe), Lausanne, Switzerland. (pdf)


2016

C42) pTask: A Smart Prefetching Scheme for OS Intensive Applications, Prathmesh Kallurkar, Smruti R. Sarangi, International Symposium on Microarchitecture (MICRO), Taipei, Taiwan. pdf, slides

C41) Leakage Power Aware Task Assignment Algorithms for Multicore Platforms, Gayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan, International Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA (pdf)

C40) SecCheck: A Trustworthy System with Untrusted Components, Rajshekar Kalayappan, Smruti R. Sarangi, International Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA (pdf)

C39) Noise Aware Scheduling in Data Centers, Hameedah Sultan, Arpit Katiyar, Smruti R. Sarangi. International Conference on Supercomputing (ICS), 2016. Istanbul. (main paper) (appendix)

C38) OptiShare: A Dynamic Channel Sharing Scheme for Power Efficient On-chip Optical Architectures, Eldhose Peter, Smruti R. Sarangi, OPTICS workshop, along with DATE 2016, Dresden, Germany. (pdf) (slides)

J14) FluidCheck: A Redundant Threading based Approach for Reliable Execution in Manycore Processors, Rajshekar Kalayappan, and Smruti R. Sarangi. ACM Transactions on Architecture and Code Optimization. Also presented in HiPEAC 2016, Prague. (pdf) (slides)

C37) A Wait-Free Stack, Seep Goel, Pooja Aggarwal, Smruti R. Sarangi, International Conference on Distributed Computing and Internet Technology (ICDCIT), Bhubaneshwar (full paper: pdf). [arxiv]

C36) A Generic Implementation of Barriers using Optical Interconnects, Sandeep Chandran, Eldhose Peter, Preeti R. Panda, Smruti R. Sarangi, VLSI Design, Kolkata (pdf)

A3) Fundamental Results for Generic Implementations of Barriers using Optical Interconnects, Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi. [arxiv]

C35) Extending Trace History Through Tapered Summaries in Post-silicon Validation, Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Deepak Chauhan, Sharad Kumar, Asia and South Pacific Design Automation Conference (ASPDAC), Macao. (pdf) (nominated for the best paper award)

J13) Active Microring Based Tunable Optical Power Splitters, Eldhose Peter, Arun Thomas, Anuj Dhawan, Smruti R. Sarangi. Optics Communications, pages 311-315 (pdf)

2015

C34) ColdBus: A Near-Optimal Power Efficient Optical Bus, Eldhose Peter, Arun Thomas, Anuj Dhawan, Smruti R. Sarangi, HiPC (High Performance Computing), Bangalore, pdf)

J12) Area-aware Cache Update Trackers for Post-silicon Validation, Sandeep Chandran, Smruti R. Sarangi, Preeti Panda, IEEE Transactions on VLSI Systems. (pdf)

C33) Tejas: A Java based Versatile Micro-architectural Simulator, Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, Eldhose Peter. PATMOS, Salvador Brazil. (pdf)

J11) Lock-free and Wait-free Slot Scheduling Algorithms by Pooja Aggarwal and Smruti R. Sarangi, IEEE Transactions on Parallel and Distributed Systems (pdf)

C32) SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators, Rajshekar Kalayappan and Smruti R. Sarangi, ISVLSI, Montpeller, France (pdf)

A2) Tejas Simulator: Validation Against Hardware, Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, arXiv:1501.07420

C31) Ethical Hacking of License Managers, Karishma Agarwal, Prathmesh Kallurkar, Siva Krishna Aleti, Smruti R. Sarangi. Security and Privacy Symposium, IIIT Delhi. (Best Poster Award) (pptx)

C30) Optimal Power Efficient Photonic SWMR Buses, Eldhose Peter, Smruti R. Sarangi, 2nd Workshop on Silicon Photonics, along with the HiPEAC Conference, Amsterdam. (pdf)

2014

J10) FP-NUCA: A Fast NOC Layer for Implementing Large NUCA Caches, Anuj Arora, Mayur Harne, Hameedah Sultan, Akriti Bagaria, Smruti R. Sarangi. IEEE Transactions on Parallel and Distributed Systems. (pdf)

C29) RADIR: Lock-free and Wait-free Bandwidth Allocation Models for Solid State Drives, Pooja Aggarwal, Giridhar Yasa, Smruti R. Sarangi, HiPC, Goa, 2014, (pdf)

C28) Optical Overlay NUCA: A High Speed Substrate for Shared L2 Caches, Eldhose Peter, Anuj Arora, Akriti Bagaria, Smruti R. Sarangi, HiPC, Goa, 2014 (pdf)

C27) Trikon: A Hypervisor Aware Manycore Processor, Rohan Bhalla, Prathmesh Kallurkar, Nitin Gupta, Smruti R. Sarangi, HiPC, Goa, 2014 (pdf)

C26) GPUTejas: A Parallel Simulator for GPU Architectures, Geetika Malhotra, Seep Goel, Smruti R. Sarangi, HiPC, Goa, 2014,  (pdf)
A1)  Three Experiments to Analyze the Nature of the Heat Spreader, arXiv:1402.6903, Seema Sethia, Shouri Chatterjee, Sunil Kale, Amit Gupta, Smruti R. Sarangi. (pdf)

C25) ParTejas: A Parallel Simulator for Multicore Processors, Geetika Malhotra, Pooja Aggarwal, Abhishek Sagar, Smruti R. Sarangi. ISPASS, Monterey, CA, USA (pdf)

J9) Processor Power Estimation Techniques: A Survey, Hameedah Sultan, Gayathri Ananthanarayanan, and Smruti R. Sarangi. International Journal of High Performance Systems Architecture. Volume 5 Issue 2, May 2014, Pages 93-114 (pdf)

C24)  Software Transactional Memory Friendly Slot Schedulers by Pooja Aggarwal, and Smruti R. Sarangi, ICDCIT, Bhubaneswar, (pdf -- extended version)

C23) OptiKit: An Open Source Kit for Simulation of On-Chip Optical Components by Eldhose Peter, and Smruti R. Sarangi. VLSI Design (Poster), Mumbai (technical report)

C22) LightSim : A Leakage Aware Ultrafast Temperature Simulator by Smruti R. Sarangi, Gayathri Ananthanarayanan, and M. Balakrishnan, ASP-DAC, Singapore (pdf)

J8) Architectural Support for Handling Jitter in Shared Memory based Parallel Applications by Sandeep Chandra, Prathmesh Kallurkar, Parul Gupta, Smruti R. Sarangi, IEEE Transactions on Parallel and Distributed Systems. Volume 25, Issue 5, May 2014 (pdf)

2013

J7) Amdahl's Law in the Era of Process Variation by Gayathri Ananthanarayanan, Geetika Malhotra, M. Balakrishnan, and Smruti R. Sarangi. International Journal of High Performance Systems Architecture (IJHPSA). 2013, Vol 4, No. 4. pp 218-230. ( pdf )

C21) A Case Study of a First-of-Its-Kind Remote Course among Premier Institutions in India by  Smruti R. Sarangi, International Conference on E-Learning and E-Technologies in Education, (ICEEE), Lodz, Poland, (pdf)

C20)  emuArm: A Tool for Teaching the ARM Assembly Language by Geetika Malhotra, Namita Atri, Smruti R. Sarangi, International Conference on E-Learning and E-Technologies in Education, (ICEEE), Lodz, Poland, (pdf)

J6) A Survey of Checker Architectures by Rajshekar Kalaiyappan and Smruti R. Sarangi, ACM Computing Surveys, Volume 45, Issue 4, Number 48 (pdf)

C19) Space Sensitive Cache Dumping for Post Silicon Validation by Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda, Design Automation and Test in Europe (DATE), Grenoble, France( pdf )

C18) Lock-free and Wait-free Slot Scheduling Algorithms by Pooja Aggarwal, Smruti R. Sarangi, International Parallel and Distributed Processing Symposium (IPDPS), Boston, USA( pdf ) (slides)

2012

C17) Efficient on-line algorithms for maintaining k-cover of a sparse bit-string by Amit Kumar, Preeti Panda, Smruti R. Sarangi, Foundations of Software Technology and Theoretical Computer Science (FSTTCS), Hyderabad, India (pdf)

J5) IT Infrastructure for Providing Energy-as-a-Service to Electric Vehicles by Smruti R. Sarangi, Partha Dutta, and Komal Jalan in IEEE Transactions on Smart Grids. (pdf)

2011

C16) UsiFe: An User Space Filesystem with Support for Intra File Encryption by Rohan Sharma, Prathmesh Kallurkar, Saurabh Kumar, and Smruti R. Sarangi, International Conference on Software and Computing Technology (ICSCT), Singapore. (pdf) (All copyrights held by SPIE)

C15) Virtualized Base Station Pool : Towards a Wireless Network Cloud for Radio Access Networks by Zhenbo Zhu, Qing Wang, Yonghua Lin, Parul Gupta, Smruti R. Sarangi Shivkumar Kalyanaraman, Hubertus Franke. ACM Computing Frontiers, Italy (pdf)

2010

C14) DUST: A Generalized Notion of Similarity between Uncertain Time Series by Smruti R. Sarangi, and Karin Murthy.Knowledge Discovery and Data Mining(KDD), Washington D.C., USA (pdf) (slides)

2009

C13) Theoretical Framework for Eliminating Redundancy in Workflows by Dhrubajyoti Saha, Abhishek Samanta, and Smruti R. Sarangi. IEEE International Conference on Service Computing (SCC), Bangalore, September 2009. (pdf)

C12) High Performance SWR Base Station and Wireless Network Cloud over General Multi-core IT Platforms by Yonghua Lin, Qing Wang, Zhenbo Zhu, Jianwen Chen, Lin Chen, Rong Yan, Wei Xie, Kuan Feng, Parul Gupta, Smruti R. Sarangi (demo paper) in MobiCom, Beijing,  2009. [link]

2008

C11) EVAL: Utilizing Processors with Variation-Induced Timing Errors by Smruti Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas. 41st International Symposium on Microarchitecture (MICRO), Lake Como, Italy, November 2008. (pdf)

J4) VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects by Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas, IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008. (pdf)

2007

J3) Patching Processor Design Errors with Programmable Hardware, Smruti R. Sarangi, Satish Naraya- naswamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas. IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture, Jan. 2007. (pdf)

C10) VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects by Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti Sarangi, Abhishek Tiwari, and Josep Torrellas (UIUC). 2nd Workshop on Architectural Support for Gigascale Integration (ASGI) (along with ISCA 2007), San Diego, USA,  June 2007. (pdf)

C9) ReCycle: Pipeline Adaptation to Tolerate Process Variation by Abhishek Tiwari, Smruti Sarangi, and Josep Torrellas, 34th Annual International Symposium on Computer Architecture (ISCA), San Diego, USA, June 2007. (pdf)

C8) Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates by Brian Greskamp, Smruti Sarangi, and Josep Torrellas. International Symposium on Circuits and Systems (ISCAS), Special Session: Circuit Design in the Presence of Device Variability, Taipei, May 2007. (pdf)

C7) A Model for Timing Errors in Processors with Parameter Variation by Smruti Sarangi, Brian Greskamp, and Josep Torrellas. 8th International Symposium on Quality Electronic Design (ISQED), March 2007. (pdf)

2006

C6) Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware by Smruti R. Sarangi, Abhishek Tiwari and Josep Torrellas. 39th International Symposium on Microarchitecture (MICRO), Dec. 2006. (pdf) (slides) (Best Paper Award)

C5) Designing Hardware that Supports Cycle-Accurate Deterministic Replay by Brian Greskamp, Smruti R. Sarangi and Josep Torrellas. Workshop on Complexity Effective Design(WCED) (along with ISCA 2006). (pdf)

C4) Rapid Prototyping in Architecture Research using Existing Hardware Mechanisms by Smruti R. Sarangi, Brian Greskamp and Josep Torrellas. Workshop on Architectural Research Prototyping(WARP) (along with ISCA 2006). (pdf)

C3) Cycle-Accurate Deterministic Replay for Processor Debugging by Smruti R. Sarangi Brian Greskamp and Josep Torrellas. Dependable Systems and Networks (DSN) 2006. (pdf)

J2) Energy-Efficient Thread-Level Speculation on a CMP by Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck and Josep Torrellas. IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture, Jan. 2006. (pdf)

2005

C2) ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing by Smruti R. Sarangi, Wei Liu, Josep Torrellas, and Yuanyuan Zhou. 38th International Symposium on Microarchitecture (MICRO), November 2005. (pdf)

C1) Thread-Level Speculation on a CMP Can Be Energy Efficient by Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. 2005 ACM International Conference on Supercomputing (ICS), June 2005. (pdf)

2003

J1) A Scalable Efficient and General Monte Carlo Scheme for Generating Synthetic Web Request Streams by Smruti R. Sarangi, P.N.Sireesh and S.P.Pal. International Journal of Computer Systems Science and Engineering, Vol. 18, pp, 121-128, May 2003. (pdf) (bibtex)