Hello
I'm Lokesh Siddhu
Ph.D. Scholar
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- ADDRESS
- 301 Research Scholars Room, 3rd Floor SIT, IIT Delhi, New Delhi 110016 (India)
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- siddhulokesh@cse.iitd.ac.in
Lokesh Siddhu is a research scholar (since Jan 2015) at the Department of Computer Science & Engg, Indian Institute of Technology, Delhi. He is pursuing his Ph.D. under the guidance of Prof. Preeti Ranjan Panda and a part of the Memory and embedded Architecture Research Group (MARG). He has a Masters' degree (Aug 2009 - Jun 2011) from Indian Institute of Science in Electronics Design And Technology. He has also worked with Intel for 3.5 years (July 2011 - Dec 2014) before joining the institute. His research interests include embedded systems, memory exploration, and optimization energy-efficient computing.
He spends his spare time by volunteering, listening to music, watching movies and doing yoga. He also likes to travel, hike and go on long drives.
External Links: Google scholar, DBLP, Linkedin, Facebook
At Intel, I have worked on the backend design of units in the server and client core. I have worked on the design (timing, quality, noise, power) of complex data-path blocks like multipliers, shifters, aligners.
Worked on the most complex block of the execution cluster (EXE). Visited Intel Haifa (Israel) to learn FMA design. Carried out studies on the different FMA designs in Intel various cores.
I quickly ramped up on various design methodologies and started owning blocks in the execution cluster (EXE) of Intel core.
CGPA: 7.3/8 (Second highest). Class Topper in 1st, 3rd Semester. Further, I studied various relevant subjects like Processor Design, Digital VLSI Circuits, Digital System Design with FPGAs and Embedded System Design.
Percentage: 80%. University topper in 3rd Semester. Studied various relevant subjects like VLSI Design, Microprocessor Design, Digital Electronics.
Latest research updates also available at Memory and embedded Architecture Research Group (MARG)
Thermal Aware Runtime Management of 3D Architecture:
Research in 3D integration has attracted researchers from industries as well as academics due to its benefits over 2D architecture such as better performance, lower power consumption, small form factor and support for heterogeneous technology integration. Furthermore, various 3D memories architectures have been proposed by industries/academia to cater to the high bandwidth requirement at low power. However, due to its higher power density and reduced heat dissipation properties, heat dissipation is one of the major challenges in the promising 3D integration technology. In this research, we aim to design thermal aware data/task mapping policies for 3D architectures.
A short write-up about my research: Click Here. See (below) a 4-minute talk that introduces my research.
Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design:
Dynamic power dissipation due to redundant switching is an important metric in datapath design. Operand isolation attempts to reduce switching by clamping or latching the output of the first level of combinational circuits. In this research, a novel method using power supply switching is proposed.
Publication: Lokesh Siddhu, Amit Mishra, and Virendra Singh. "Operand Isolation with Reduced Overhead for Low Power Datapath Design," VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on. IEEE, 2014.
Conference Volunteering
Volunteer coordinator for VLSID 2019 (held at New Delhi, General Chair - Prof. Preeti Ranjan Panda) jointly with Rajesh Kedia. Handled various aspects of conference planning and organization, including
Collaboration
I have regularly collaborated with Rajesh Kedia and also worked with Ph.D. students (Aritra Bagchi, Isaar Ahmed, Shailja Pandey) to discuss research problems and appropriate experimentation infrastructure.
Technical Service
I have been frequently reviewing papers for the following forums: ASPDAC, CODES+ISSS, DAC, DATE, ESL, ISLPED, IPDPS, TCAD, TODAES, TPDS, VDAT, VLSID.
Conferences Attended
Attended the following conferences: Embedded Systems Week (ESW) 2020, ISLPED 2020, VLSID (2016-2020), ESW 2019, DATE 2019.
Research Seminar Series
Organized more than ten research seminars (approx. 45-minute talks by Ph.D. students) to enable more interaction of students from various research fields, primarily within Computer Science.
Have done the following courses (mentioned in reverse chronological order). My current CGPA is 9.48 (out of 10.0)
Compiler Design by Preeti R. Panda, System-Level Design and Modeling by M. Balakrishnan, Analysis and Design of Algorithms (Audit) by Amit Kumar
Operating Systems by Sorav Bansal, Architechture of Large Systems by Anshul Kumar, Communication Skills by Akash Raha
I have contributed in the following ways: involvement in the definition of lab exercises, implementing an automated evaluation system using Moodle VPL and orientating/coordinating with other TAs. In my TA-work, I have been focussing on methods to ensure uniformity of evaluation, and provide timely feedback (and query redressal) to the students.
COL812: System Level Design and Modelling (High-level Design and Modelling) by Preeti R. Panda.
CJL216: Computer Architechture (IIT Jammu) by Preeti R. Panda.
Synthesis of Digital Systems (NPTEL) by Preeti R. Panda.
COP701: Software Systems Laboratory by Huzur Saran
Received Honourable Mention for TA work.
301 Research Scholars Room, 3rd Floor SIT,
IIT Delhi, New Delhi 110016 (India)
