Journals

  1. Providing Accountability in Heterogeneous SOCs
    Rajshekar Kalayappan, Smruti R. Sarangi
    ACM Transactions on Embedded Computing Systems (TECS) (submitted)
  2. ParTejas : A Parallel Simulator for Multicore Processors (pdf)
    Geetika Malhotra, Rajshekar Kalayappan, Seep Goel, Pooja Aggarwal, Abhishek Sagar, Smruti R. Sarangi
    ACM Transactions on Modeling and Computer Simulation (TOMACS). Volume 27 Issue 3, August 2017.
  3. FluidCheck: A Redundant Threading-Based Approach for Reliable Execution in Many-core Processors (pdf)
    Rajshekar Kalayappan, Smruti R. Sarangi
    ACM Transactions on Architecture and Code Optimization (TACO). Volume 12 Issue 4, January 2016.

    Presented at European Network on High Performance and Embedded Architecture and Compilation Conference (HiPEAC'16), Prague, Czech Republic, 2016.
  4. Surveillance using non-stealthy sensors: A new intruder model (pdf)
    Amitabha Bagchi, Rajshekar Kalayappan, Surabhi Sankhla
    Wiley Security and Communication Networks. Volume 7, Issue 11, November 2014.
  5. A survey of checker architectures (pdf)
    Rajshekar Kalayappan, Smruti R. Sarangi
    ACM Computing Surveys (CSUR). Volume 45, Issue 4, August 2013.

Conferences

  1. Parallelizing the Simulation of Serial Benchmarks
    Rajshekar Kalayappan, Avantika Chhabra, Smruti R. Sarangi (to be submitted)
  2. A Hardware Implementation of the kCAS Synchronization Primitive (pdf)
    Srishty Patel, Rajshekar Kalayappan, Ishani Mahajan, Smruti R. Sarangi
    Design, Automation and Test in Europe (DATE'17), Lausanne, Switzerland, 2017.
  3. SecCheck : A Trustworthy System with Untrusted Components (pdf)
    Rajshekar Kalayappan, Smruti R. Sarangi
    IEEE Computer Society Annual Symposium on VLSI (ISVLSI'16), Pittsburgh, USA, 2016.
  4. SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators (pdf)
    Rajshekar Kalayappan, Smruti R. Sarangi
    IEEE Computer Society Annual Symposium on VLSI (ISVLSI'15), Montpellier, France, 2015.
  5. Tejas: A java based versatile micro-architectural simulator (pdf)
    Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, Eldhose Peter
    IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'15), Salvador, Brazil, 2015.

Patents

  1. Parallelization of a Trace-Driven Architectural Simulator
    Smruti R. Sarangi, Rajshekar Kalayappan, Avantika Chhabra (under process)
  2. Providing Accountability in Heterogeneous SoCs Using Dual Metering
    Smruti R. Sarangi, Rajshekar Kalayappan (under process)