Rajshekar K is a Senior Research Fellow at the Indian Institute of Technology Delhi, working on techniques to parallelize an architectural simulator. He has submitted his PhD thesis at the same institute, under the guidance of Dr. Smruti Ranjan Sarangi. His thesis is titled "Employing Redundancy Techniques to Provide Reliability, Security and Accountability in Modern Processors".

His research interests include computer architecture, hardware reliability, hardware security, accountability issues in heterogeneous 3PIP-containing SOCs, and microarchitectural simulation.

He is one of chief designers, developers and maintainers of the popular open source architectural simulator Tejas. Tejas simulates state-of-the-art multi-core processors. Tejas has been made open source under the Apache v2 license. It is used in many universities, in India and across the globe, for both teaching and research purposes. It has been validated against real hardware, and is at par with the best academic simulators in terms of simulation speed. Please visit the Tejas web page to know more.

He is nearing the completion of his PhD (thesis submitted in December 2016), and is looking for both academic and industry positions.

Curriculum Vitae