Tutorials, Invited Talks, and Keynote Addresses

Conference Tutorials

  1. Scratch Pad Memory - Managing Local Memory in Software , Tutorial at Intl. Conf. on VLSI and Signal Processing, IIT Kharagpur, Jan 2014
  2. System \& RTL Low Power Design , Preeti Ranjan Panda, Subrangshu Das, S. Jairam, Abhishek Ranjan, Nikhil Tripathi, and Sanjiv Narayan, International Conference on VLSI Design (VLSI Design), Pune, January 2013
  3. Memory Architectures and Software Transformations for System Level Design , Preeti Ranjan Panda and Stylianos Mamagkakis, Asia and South Pacific Design Automation Conference (ASP-DAC'09), Yokohama, January 2009
  4. Specification and Design of Multimillion Gate SOCs , Ramesh Chandra, Joerg Henkel, Preeti Ranjan Panda, Sridevan Parameswaran, and Loganath Ramachandran, The 16th International Conference on VLSI Design (VLSI Design '03), New Delhi, January 2003
  5. Specification and Design of Multimillion Gate SOCs , Ramesh Chandra, Joerg Henkel, Preeti Ranjan Panda, Sridevan Parameswaran, and Loganath Ramachandran, IEEE/ACM International Conference on Computer Aided Design (ICCAD '02), San Jose, November 2002
  6. Embedded Memories in System Design: Technology, Application, Design and Tools , Doris Keitel-Shulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda, and Nikil Dutt, International Conference on VLSI Design (VLSI Design'01), Bangalore, January 2001

Invited Talks/Seminars

  1. Runtime Co-optimisation in the Memory Hierarchy, Workshop on Memory and Storage Systems (WoMS), IIT Gandhinagar, December 2017
  2. Runtime Co-optimisation of Cores, Caches, and On-chip Network, The University of Tokyo, August 2017
  3. Runtime Co-optimisation of Cores, Caches, and On-chip Network, Ritsumeikan University, August 2017
  4. Moore's Law meets Murphy's Law: Design-for-Debug in Modern Architectures, NXP Semiconductor, Apr 2017
  5. Runtime Resource Adaptation: Simultaneous Optimisation of Cores, Caches, and On-chip Network, Hong Kong Polytechnic University, Aug 2016
  6. Software Caches - Emulating Cache Behaviour in Software, Technical University of Munich, November 2015
  7. Memory Architecture Reconfiguration and Exploration (Keynote Address), Synopsys University Symposium, New Delhi, 30 April 2015
  8. Compiler-directed Local Memory Reconfiguration , Intel, Bangalore, January 2015
  9. Advanced Debug Architecture and Methodology for Heterogeneous Multi-core Platforms, Semiconductor Research Corporation GRC e-Workshop, 9 Dec 2014
  10. Software Caches - Emulating Cache Behaviour in Software, Carnegie-Mellon University, May 2014
  11. Software Caches - Emulating Cache Behaviour in Software, Pennsylvania State University, May 2014
  12. Compiler-directed Local Memory Reconfiguration, Xilinx, Inc., San Jose, May 2014
  13. Software Caches - Emulating Cache Behaviour in Software, Freescale, Noida, January 2013
  14. Software Caches - Emulating Cache Behaviour in Software, Seoul National University, Seoul, December 2012
  15. Software Caches - Emulating Cache Behaviour in Software, Memory Architecture and Organization Workshop (MeAOW at Embedded Systems Week), Tampere, Finland, Oct 2012
  16. Software Caches and Scratch Pad Memory - Orchestrating Memory at Higher Abstraction Levels in Low Power Embedded Systems, Samsung Research Network Meeting, May 2012
  17. Energy Efficiency in Graphics Rendering, Stanford University, February 2012
  18. Energy Efficiency in Graphics Rendering, Technical University of Dortmund, June 2011
  19. Introducing Energy Efficiency into Graphics Processors, Calypto Design Systems, Noida, February 2011
  20. Cache Compression for Post-Silicon Processor Debug, IMEC, Leuven, Belgium, July 2010
  21. Cache Compression for Post-Silicon Processor Debug, EPFL, Lausanne, Switzerland, July 2009
  22. Cache Compression for Post-Silicon Processor Debug, National University of Singapore, Singapore, July 2009
  23. Post-Silicon Processor Validation/Debug: Introduction and Research Directions, DRDO ANURAG Lab, Hyderabad, June 2009
  24. Cache Compression for Post-Silicon Processor Debug, Karlsruhe University, Karlsruhe, Germany, April 2009
  25. Cache Compression for Post-Silicon Processor Debug, NXP Semiconductors, Bangalore, April 2009
  26. Power Optimisations in Embedded Systems: Register File and Memory Hierarchy, TECCI - Technical Conference of Cadence India, April 2007
  27. Fast Cache Dump for Processor Debug, Indian Semiconductor Association (ISA) Vision Summit, Hyderabad, February 2007
  28. Who Killed Behavioural Synthesis?, Intel Technology India Pvt. Ltd., Bangalore, April 2007
  29. Low Power Register File Architectures, Sequence Design, Noida, March 2007
  30. High Level Synthesis, Workshop on System Level Design and Modelling, February 2007
  31. Who Killed Behavioural Synthesis?, Cadence, Noida, February 2007
  32. Models of Specification in Embedded Systems, Workshop on System Level Design and Modelling, February 2007
  33. Models of Specification for Embedded Systems, Workshop on Embedded Systems, MNIT, Jaipur, December 2006
  34. Customizing Memory Architectures in Embedded Systems, 11th International Conference on High Performance Computing (HiPC'04) - Workshop on Performance Improvement of Mobile Devices, Bangalore, December 2004
  35. The role of EDA industry in VLSI research, Magma User Summit on Integrated Circuits (MUSIC'04), Bangalore, August 2004
  36. Incorporating Memory in Embedded Systems: Modelling, Optimisation, and Customisation (Keynote Address), Workshop on Reconfigurable Computing using FPGAs, MNIT, Jaipur, February 2004
  37. VLSI Synthesis, Centre for Development of Advanced Computing (C-DAC), Noida, June 2003, Dec 2003
  38. The energy impact of memory port allocation decisions, VLSI Design and Test Workshop (VDAT'03), Bangalore, August 2003
  39. Memory Architectures for Embedded Systems-on-Chip, Preeti Ranjan Panda and Nikil Dutt, 9th International Conference on High Performance Computing (HiPC 2002), December 2002
  40. Memory Optimizations in Embedded Systems, Embedded Systems Design Workshop, IIT Delhi, January 2002
  41. SystemC -- A modeling platform supporting multiple design abstractions, International Symposium on System Synthesis (ISSS '01), Montr\'eal, October 2001
  42. The SystemC Design Language , Xilinx, San Jose, 2001
  43. Application Specific Memory Customization, SSGRR International Conference on Advances in Computer Infrastructure, L'Aquila, Italy, July/August 2000

Keynote Addresses

  1. Memory Architecture Reconfiguration and Exploration , Synopsys University Symposium, New Delhi, 30 April 2015
  2. Incorporating Memory in Embedded Systems: Modelling, Optimisation, and Customisation, Workshop on Reconfigurable Computing using FPGAs, MNIT, Jaipur, February 2004
Copyright (C) 2016 P. R. Panda
Original design by Dreamtemplatestudio