Research
Embedded Systems...Architecture...Low Power Design...EDA...
We are involved in several fascinating research projects related to the topic of embedded systems, architecture, low power design, and electronic design automation. We actively collaborate with the industry in the formulation and execution of research problems.
Low Power Graphics Processors
Graphics processors (GPUs) are powerful processors that consume about the same power as typical high-end CPUs in modern computer systems, yet architecture-level power optimisation research has almost completely focussed on the CPU. We are exploring low power mechanisms based on dynamic voltage and frequency scaling (DVFS) and improvements to the standard texture cache hierarchy. [Sponsor: Intel]Relevant Publications:
- Rank Based Dynamic Voltage and Frequency Scaling for Tiled Graphics Processors
B. V. N. Silpa, Gummidipudi Krishnaiah, and Preeti Ranjan Panda
(CODES+ISSS), Scottsdale, USA, October 2010 (Best Paper Candidate) - Texture Filter Memory: A Power-efficient and Scalable Texture Memory Architecture for Mobile Graphics Processors , B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran, IEEE/ACM International Conference on Computer Aided Design (ICCAD '08), San Jose, November 2008
Improving Emulation Efficiency
FPGA emulation of complex processors is necessary because of the need to perform fast system simulations. In recent reseach, we have investigated the acceleration of trace-based on-chip interconnect emulation. [Sponsor: Intel]Relevant Publications:
- FastFwd: An Efficient Hardware Acceleration Technique for Trace-driven Network-on-Chip Simulation
Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, and Anshul Kumar
(CODES+ISSS), Scottsdale, USA, October 2010
Post-silicon Processor Validation/Debug
During post-silicon processor validation, the state of the processor needs to be dumped out to a logic analyser so as to enable debug. Since the state is large (mostly L2 cache) and a lot of time is spent in the process of dumping, we have designed a compression mechanism that compresses debug data on its way out of the processor. Knowledge of the cache architecture is used to achieve high compression ratios, resulting in saving of logic analyser memory and dump time. [Sponsor: Intel]Relevant Publications:
- Compressing Cache State for Post-Silicon Processor Debug
Preeti Ranjan Panda, M. Balakrishnan, and Anant Vishnoi
IEEE Transactions on Computers (TOC), 2010 (accepted for publication) - Online Cache State Dumping for Processor Debug
A. Vishnoi, Preeti Ranjan Panda, and M. Balakrishnan
Design Automation Conference (DAC'09), San Francisco, USA, July 2009 - Cache Aware Compression for Processor Debug Support, A. Vishnoi, Preeti Ranjan Panda, M. Balakrishnan, Design Automation and Test in Europe (DATE'09), Nice, April 2009
Behavioural Synthesis
Behavioural Synthesis (or High-Level Synthesis - HLS) seeks to automatically generate hardware from higher levels of design abstraction. Although research in this area is more than two decades old, serious commercial solutions are only just appearing on the horizon ( Article in CEDA Newsletter, August 2008). Our recent work in HLS has concentrated on issues around achieving timing accuracy. Estimating FSM delays (DAC'06) and making intelligent loop unrolling choices (DATE'07) are some specific problems we have addressed.Relevant Publications:
- Rapid estimation of control delay from high-level specifications, Gagan Raj Gupta, Madhur Gupta, and Preeti Ranjan Panda, 43rd Design Automation Conference (DAC '06), San Francisco, USA, July 2006
- The Impact of Loop Unrolling on Controller Delay in High Level Synthesis, Srikanth Kurra, Neeraj K Singh and Preeti Ranjan Panda, Design Automation and Test in Europe (DATE'07), Nice, France, April 2007
Memories in Embedded Systems
Embedded systems offer the exciting opportunity to customise system architectures according to the requirements of the application. In our research work, we have investigated ways to customise different aspects of the memory subsystem in embedded systems. In earlier work at UC Irvine, we introduced the concept of Scratch Pad Memory and investigated ways to partition on-chip data memory space between scratch pad memory and data cache (ED&TC'1997, TODAES-July'00, ISSS'97, TCAD-Jan'99). Other memory-related problems we have addressed relate to low power memory mapping (TVLSI-Sep'99), cache-aware data placement (TOC-Feb'99, TODAES-Oct'97), DRAM in synthesis (TCAD-Feb'98).The book Memory issues in Embedded Systems-on-chip and our survey articles in TODAES-April'01 and D& T-May/June'01 capture some of the recent developments on data memory optimisations in embedded systems.
Selected Relevant Publications:
- Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration, Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau, Kluwer Academic Publishers, Norwell, MA, 1999.
- Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications, Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau, European Design and Test Conference (ED & TC '97), Paris, March 1997
- Data and memory optimization techniques for embedded systems (Survey/Tutorial paper) P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, and P. G. Kjeldsberg, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 6, No. 2, April 2001
- On chip vs. off chip memory: the data partitioning problem in embedded processor-based systems , Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 5, No. 3, July 2000
