Current PhD Students
Neetu Jindal (Jointly supervised by Smruti R. Sarangi)
Hadi Brais
Lokesh Siddhu
Sakshi Tiwari
Divya Praneetha
Graduated PhD Students
Sandeep Chandran (2017. Now at AMD. Jointly supervised by Smruti R. Sarangi)
Rahul Jain (2017. Now at Reniac.
Prasenjit Chakraborty (2015. Now at Intel.)
Namita Sharma (2015. Now at Intel.)
Vaibhav Jain (2015. Now at DAVV. Jointly supervised by Anshul Kumar.)
Krishnaiah Gummidipudi (2013. Now at Intel. Jointly supervised by Anshul Kumar.)
B. V. N. Silpa (2012. Now at Nvidia.)
Neeraj Goel (2012. Now at IIT Ropar. Jointly supervised by Anshul Kumar.)
Anant Vishnoi (2010. Now at Cadence. Jointly supervised by M. Balakrishnan.)
Aryabartta Sahu (2010. Now at IIT Guwahati. Jointly supervised by M. Balakrishnan.)

Shared Cache Management and Machine Learning-enhanced Architecture

Collaborator: Intel and Semiconductor Research Corporation (SRC)

The shared cache levels of the memory hierarchy present many opportunities in modern Multiprocessor Systems-on-Chip (MPSoCs) for intelligent control and management. We have employed machine learning techniques to perform intelligent runtime adaptation of CPU system resources through a fine-grained orchestration of cache partitioning at multiple levels and frequency control of the CPU and on-chip network.

Smartphone Energy Efficiency

Collaborator: Samsung

Modern smartphones constitute a platform for intricate trade-offs between performance and power/energy. Dynamic Voltage and Frequency Scaling (DVFS) techniques help aggressively reduce power consumption, but also affect performance negatively. In this ongoing research collaboration with Samsung, we are formulating and evaluating novel techniques for saving energy in Android phones while meeting performance requirements. Our book Power-efficient System Design surveys power-efficiency and energy-efficiency at different abstraction levels in computing systems.

Post-silicon Validation

Collaborator: Freescale and Semiconductor Research Corporation (SRC)

As the computer industry moves towards the era of multi-core and many-core SoCs with a large number of processor cores and accelerators, there is an urgent need for revamping the post-silicon validation methodologies, and re-architecting the hardware debug mechanisms. Robust validation methodologies play a vital role in the chip design flow, as the industry struggles to contain costs under increasing design complexity. In this research we attempt a scalable debug methodology that is sensitive to the requirements of handling large amounts of debug data with area constraints, and explore the possibility of reusing debug hardware to improve performance.

Memory Exploration and Optimisation

Collaborators: IBM, IMEC

In earlier work, we introduced the concept of Scratch Pad Memory (SPM) (P. R. Panda, N. D. Dutt, A. Nicolau, Efficient utilization of scratch-pad memory in embedded processor applications. ED&TC 1997) and investigated ways to partition on-chip data memory space between scratch pad memory and data cache. The book Memory issues in Embedded Systems-on-chip captures some of the recent developments on data memory optimisations in embedded systems. Our paper Data and memory optimization techniques for embedded systems (ACM TODAES, Apr 2001) has been the most downloaded paper of the journal for several years. As memory technologies evolve, we continue to investigate different ensuing system-level research problems: Non-volatile and 3D memories, software caches, data layout, SPM with vector registers, etc.

Other Research Topics

  • Power-efficiency in Graphics Processors
  • Accelerating NoC Emulation
  • High-level Synthesis

Thanks to Our Sponsors:

  • Intel
  • IBM
  • Freescale Semiconductor
  • Samsung
  • Semiconductor Research Corporation
  • Calypto Design Systems
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