Current PhD Students
Hadi Brais
Lokesh Siddhu
Sakshi Tiwari
Divya Praneetha
Isaar Ahmad
Aritra Bagchi
Ayushi Agarwal
Garima Modi
Shailja Pandey
Graduated PhD Students
Neetu Jindal (2019. Joined Intel. Jointly supervised by S. R. Sarangi.)
Sandeep Chandran (2018. Joined IIT Palakkad. Jointly supervised by S. R. Sarangi.)
Rahul Jain (2017. Joined Reniac.)
Prasenjit Chakraborty (2015. Joined Intel.)
Namita Sharma (2015. Joined Intel.)
Vaibhav Jain (2015. Joined DAVV. Jointly supervised by Anshul Kumar.)
Krishnaiah Gummidipudi (2013. Joined Intel. Jointly supervised by Anshul Kumar.)
B. V. N. Silpa (2012. Joined Nvidia.)
Neeraj Goel (2012. Joined IIT Ropar. Jointly supervised by Anshul Kumar.)
Anant Vishnoi (2010. Joined Cadence. Jointly supervised by M. Balakrishnan.)
Aryabartta Sahu (2010. Joined IIT Guwahati. Jointly supervised by M. Balakrishnan.)
Research

Shared Cache Management

Collaborator: Intel and Semiconductor Research Corporation (SRC)

The shared cache levels of the memory hierarchy present many opportunities in modern Multiprocessor Systems-on-Chip (MPSoCs) for intelligent control and management. We have employed machine learning techniques to perform intelligent runtime adaptation of CPU system resources through a fine-grained orchestration of cache partitioning at multiple levels and frequency control of the CPU and on-chip network. Our recent work in this area has targeted the novel problem of cache bandwidth partitioning.

Project website for Machine Learned Machines including experimental platform software.

Hardware Architectures for AI/Machine Learning

Collaborator: Cadence Design Systems

The popularity AI/ML applications has led to various hardware architectures targeting their efficient execution. The existence of hardware ML accelerators leads to several novel research problems related to the co-optimisation of the CPUs along with the accelerators. In this large IITD project sponsored by Cadence Design Systems, we are investigating hardware architectural schemes for efficient ML computations in Edge devices.

Emerging Memory Technologies: 3D and Non-volatile Memory

The search is on for the next generation high-density and high-bandwidth memory technologies. We are studying non-volatile memories (PCM, STT-RAM) and 3D DRAM structures. 3D memory offers the advantages of high bandwidth and density, but incurs thermal problems. We are researching ways to maximise 3D memory system performance while respecting temperature constraints.

Post-silicon Validation

Collaborator: Freescale/NXP and Semiconductor Research Corporation (SRC)

As the computer industry moves towards the era of multi-core and many-core SoCs with a large number of processor cores and accelerators, there is an urgent need for revamping the post-silicon validation methodologies, and re-architecting the hardware debug mechanisms. Robust validation methodologies play a vital role in the chip design flow, as the industry struggles to contain costs under increasing design complexity. In this research we attempt a scalable debug methodology that is sensitive to the requirements of handling large amounts of debug data with area constraints, and explore the possibility of reusing debug hardware to improve performance.

Memory Organisation and Energy/Power Efficiency

Collaborators: IBM, IMEC

In earlier work, we introduced the concept of Scratch Pad Memory (SPM) (P. R. Panda, N. D. Dutt, A. Nicolau, Efficient utilization of scratch-pad memory in embedded processor applications. ED&TC 1997) and investigated ways to partition on-chip data memory space between scratch pad memory and data cache. The book Memory issues in Embedded Systems-on-chip captures some of the recent developments on data memory optimisations in embedded systems. Our paper Data and memory optimization techniques for embedded systems (ACM TODAES, Apr 2001) has been the most downloaded paper of the journal for several years. Our book Power-efficient System Design surveys power-efficiency and energy-efficiency at different abstraction levels in computing systems.

Other Research Topics

  • Power-efficiency in Graphics Processors
  • Accelerating NoC Emulation
  • High-level Synthesis

Thanks to Our Sponsors:

  • Cadence Design Systems
  • Calypto Design Systems
  • Freescale Semiconductor/NXP Semiconductors
  • IBM
  • Intel
  • Samsung
  • Semiconductor Research Corporation
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