BOOKS

Book Cover: Power-efficient System Design

NEW: Power-efficient System Design
Preeti Ranjan Panda, Aviral Shrivastava, B. V. N. Silpa, Krishnaiah Gummidipudi
Springer, New York, 2010.

Book Cover: Memory Issues in Embedded Systems-On-Chip: Optimizations and
Exploration

Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
Kluwer Academic Publishers, Norwell, 1999.

BOOK CHAPTERS

Power Optimisation Strategies Targeting the Memory Subsystem
Preeti Ranjan Panda
in Designing Embedded Processors - A Low Power Perspective (eds. Jorg Henkel and Sri Parameswaran)
Springer, pp131-155, 2007
Improving Cache Performance through Tiling and Data Alignment
Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau
Lecture Notes in Computer Science (LNCS) Vol. 1253, Springer-Verlag, 1997, pp. 167-185
Memory Architectures for Embedded Systems-on-Chip
Preeti Ranjan Panda and Nikil Dutt
Lecture Notes in Computer Science (LNCS) Vol. 2552, Springer-Verlag, 2002, pp. 647-662

JOURNAL PAPERS

Compressing Cache State for Post-Silicon Processor Debug
Preeti Ranjan Panda, M. Balakrishnan, and Anant Vishnoi
IEEE Transactions on Computers (TOC), 2010 (accepted for publication)
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, and Anshul Kumar
International Journal of Parallel Programming (IJPP), Vol. 35, No. 6, pp507-527, 2007
Memory Allocation and Mapping in High-level Synthesis: An Integrated Approach
Jaewon Seo, Taewhan Kim, and Preeti Ranjan Panda
IEEE Transactions on VLSI Systems (T-VLSI), Vol. 11, No. 5, October 2003
Data Memory Organization and Optimizations in Application-Specific Systems
P. R. Panda, N. D. Dutt, A. Nicolau, F. Catthoor, A. Vandecappelle, E. Brockmeyer, C. Kulkarni, and E. de Greef
IEEE Design and Test of Computers (D & T), Vol. 18, No. 3, May/June 2001.
Data and memory optimization techniques for embedded systems (Survey/Tutorial paper)
P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, and P. G. Kjeldsberg
ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 6, No. 2, April 2001
On chip vs. off chip memory: the data partitioning problem in embedded processor-based systems
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 5, No. 3, July 2000
Low Power Memory Mapping through Reducing Address Bus Activity
Preeti Ranjan Panda and Nikil D. Dutt
IEEE Transactions on VLSI Systems (T-VLSI), Vol. 7, No. 3, September 1999
High-Level Synthesis with SDRAMs and RAMBUS DRAMs
Asheesh Khare, Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Vol. E82A, No. 11, pp 2347-2355, 1999
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance
Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau
IEEE Transactions on Computers (TOC), Vol 48, No. 2, February 1999
Local Memory Exploration and Optimization in Embedded Systems
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T-CAD), Vol 18, No. 1, January 1999.
Incorporating DRAM Access Modes in High-Level Synthesis
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T-CAD), Vol 17, No. 2, February 1998
Memory Data Organization for Improved Cache Performance in Embedded Processor Applications
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 2, No. 4, October 1997
Estimating the complexity of synthesized designs from FSM Specifications
Biswadip Mitra, Preeti Ranjan Panda, and P. Pal Chaudhary
IEEE Design & Test of Computers (D & T) , March 1993

CONFERENCE PAPERS

FastFwd: An Efficient Hardware Acceleration Technique for Trace-driven Network-on-Chip Simulation
Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, and Anshul Kumar
(CODES+ISSS), Scottsdale, USA, October 2010
Rank Based Dynamic Voltage and Frequency Scaling for Tiled Graphics Processors
B. V. N. Silpa, Gummidipudi Krishnaiah, and Preeti Ranjan Panda
(CODES+ISSS), Scottsdale, USA, October 2010 (Best Paper Candidate)
Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine
B. V. N. Silpa, Kumar S. S. Vemuri, and Preeti Ranjan Panda
International Symposium on Visual Computing (ISVC (1))(LNCS 5785), Las Vegas, USA, November 2009, pp 111-124
Online Cache State Dumping for Processor Debug
A. Vishnoi, Preeti Ranjan Panda, and M. Balakrishnan
Design Automation Conference (DAC'09), San Francisco, USA, July 2009
Cache Aware Compression for Processor Debug Support
A. Vishnoi, Preeti Ranjan Panda, and M. Balakrishnan
Design, Automation and Test in Europe (DATE'09), Nice, France, April 2009
A Generic Platform for Estimation of Multi-threaded Program Performance on Heterogeneous Multiprocessor
A. Sahu, M. Balakrishnan, and Preeti Ranjan Panda
Design, Automation and Test in Europe (DATE'09), Nice, France, April 2009
Texture Filter Memory: A Power-efficient and Scalable Texture Memory Architecture for Mobile Graphics Processors
B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, and G. S. Visweswaran
IEEE/ACM International Conference on Computer Aided Design (ICCAD '08), San Jose, November 2008
Unified Modeling Abstraction for Fast Simulation and Emulation
G. Krishnaiah, Preeti Ranjan Panda, Ashok Janannathan, Sreenivas Subramoney, and Anshul Kumar
3rd Workshop on Architectural Research Prototyping (WARP'08), Beijing, China, June 2008
REWIRED - Register Write Inhibition by Resource Dedication
Pushkar Tripathi, Rohan Jain, Srikanth Kurra, and Preeti Ranjan Panda
13th Asia and South Pacific Design Automation Conference (ASPDAC '08), Seoul, Korea, pp28-31, January 2008
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform
Rahul Jain and Preeti Ranjan Panda
Intl. Symposium on Circuits and Systems (ISCAS'07), New Orleans, May 2007
The Impact of Loop Unrolling on Controller Delay in High Level Synthesis
Srikanth Kurra, Neeraj K Singh and Preeti Ranjan Panda
Design Automation and Test in Europe (DATE'07), Nice, France, April 2007
Power Reduction in VLIW Processor with Compiler Driven Bypass Network
Neeraj Goel, Anshul Kumar and Preeti Ranjan Panda
Intl. Conference on VLSI Design and Embedded Systems (VLSI'07), Bangalore, Jan 2007
Customization of Register File Banking Architecture for Low Power
Rakesh Nalluri, Rohan Garg and Preeti Ranjan Panda
Intl. Conference on VLSI Design and Embedded Systems (VLSI'07), Bangalore, Jan 2007
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
Rahul Jain and Preeti Ranjan Panda
Intl. Conference on VLSI Design and Embedded Systems (VLSI'07), Bangalore, Jan 2007
Energy efficient application specific banked register files
Rakesh Nalluri and Preeti Ranjan Panda
10th IEEE VLSI Design and Test Symposium (VDAT '06), Goa, August 2006, pp56-65
A power efficient architecture for 2-D Discrete Wavelet Transform
Rahul Jain and Preeti Ranjan Panda
10th IEEE VLSI Design and Test Symposium (VDAT '06), Goa, August 2006, pp121-129
Rapid estimation of control delay from high-level specifications
Gagan Raj Gupta, Madhur Gupta, and Preeti Ranjan Panda
43rd Design Automation Conference (DAC '06), San Francisco, USA, July 2006, pp455-458
Abridged Addressing: A Low Power Memory Addressing Strategy
Preeti Ranjan Panda
11th Asia and South Pacific Design Automation Conference (ASPDAC '06), Yokohama, Japan, January 2006, pp892-897
A technique for predicting the effect of data cache associativity
Viresh Kumar and Preeti Ranjan Panda
9th IEEE VLSI Design and Test Symposium (VDAT '05), Bangalore, August 2005, pp259-268
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, and Anshul Kumar
Design Automation and Test in Europe (DATE '05), Munich, March 2005, pp730-735
Extracting Exact Finite State Machines from Behavioral SystemC Descriptions
Vikram Singh Saun and Preeti Ranjan Panda
18th International Conference on VLSI Design (VLSI Design '05), Kolkata, January 2005, pp280-285
Memory Architectures for Embedded Systems-on-Chip (invited paper)
Preeti Ranjan Panda and Nikil Dutt
9th International Conference on High Performance Computing (HiPC 2002), December 2002
An Energy-conscious Algorithm for Memory Port Allocation
Preeti Ranjan Panda and Lakshmikantam Chitturi
IEEE/ACM International Conference on Computer Aided Design (ICCAD '02), San Jose, November 2002
An Integrated Algorithm for Memory Allocation and Assignment in High-level Synthesis
Jaewon Seo, Taewhan Kim, and Preeti Ranjan Panda
39th Design Automation Conference (DAC '02), New Orleans, June 2002
SystemC - A modeling platform supporting multiple design abstractions (invited paper)
Preeti Ranjan Panda
International Symposium on System Synthesis (ISSS '01), Montreal, October 2001
Cache-efficient memory layout of aggregate data structures
Preeti Ranjan Panda, Luc Semeria, and Giovanni de Micheli
International Symposium on System Synthesis (ISSS '01), Montreal, October 2001
Application Specific Memory Customization (invited paper)
Preeti Ranjan Panda
SSGRR International Conference on Advances in Computer Infrastructure, L'Aquila, Italy, July/August 2000
Memory Bank Customization and Assignment in Behavioral Synthesis
Preeti Ranjan Panda
IEEE/ACM International Conference on Computer Aided Design (ICCAD '99), San Jose, November 1999
High-Level Synthesis with Synchronous and RAMBUS DRAMs
Asheesh Khare, Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
The Eighth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'98), Sendai, Japan, October 1998
Data Cache Sizing for Embedded Processor Applications
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
Design Automation and Test in Europe (DATE'98), Paris, February 1998, pp925-926
Exploiting Off-Chip Memory Access Modes in High-Level Synthesis
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
IEEE/ACM International Conference on Computer Aided Design (ICCAD '97), San Jose, November 1997
A Data Alignment Technique for Improving Cache Performance
Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau
International Conference on Computer Design (ICCD '97), Austin, October 1997
Architectural Exploration and Optimization of Local Memory in Embedded Systems
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
International Symposium on System Synthesis (ISSS '97), Antwerp, September 1997
Improving Cache Performance through Tiling and Data Alignment
Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau
The 4th International Symposium on Solving Irregularly Structured Problems in Parallel (IRREGULAR'97), Paderborn, June 1997
Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
European Design and Test Conference (ED & TC '97), Paris, March 1997
Behavioral Array Mapping into Multiport Memories Targeting Low Power
Preeti Ranjan Panda and Nikil D. Dutt
10th International Conference on VLSI Design (VLSI Design '97), Hyderabad, January 1997
Memory Organization for Improved Data Cache Performance in Embedded Processors
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
International Symposium on System Synthesis (ISSS '96), La Jolla, November 1996
Low Power Mapping of Behavioral Arrays to Multiple Memories
Preeti Ranjan Panda and Nikil D. Dutt
International Symposium on Low Power Electronics and Design (ISLPED '96), Monterey, August 1996
Reducing Address Bus Transitions for Low Power Memory Mapping
Preeti Ranjan Panda and Nikil D. Dutt
European Design and Test Conference (ED & TC '96), Paris, March 1996
1995 High Level Synthesis Design Repository
Preeti Ranjan Panda and Nikil D. Dutt
International Symposium on System Synthesis (ISSS '95), Cannes, September 1995
Fibre Channel Protocol: Formal Specification and Verification
Vijay Nagasamy, Sreeranga Rajan, and Preeti Ranjan Panda
Silicon Valley Networking Conference (SVNC '95), San Jose, April 1995
Estimating the complexity of synthesized designs from FSM Specifications
Biswadip Mitra, Preeti Ranjan Panda, and P. Pal Chaudhary
5th International Conference on VLSI Design (VLSI Design '92), Bangalore, Jan 1992 (Honourable Mention Award)
A Flexible Scheme for State Assignment Based on Characteristics of the FSM
Biswadip Mitra, Preeti Ranjan Panda, and P. Pal Chaudhary
International Conference on Computer Aided Design (ICCAD '91), Santa Clara, November 1991

TUTORIALS

Memory Architectures and Software Transformations for System Level Design
Stylianos Mamagkakis and Preeti Ranjan Panda
Asia and South Pacific Design Automation Conference (ASPDAC '09), Yokohama, January 2009
Specification and Design of Multimillion Gate SOCs
Ramesh Chandra, Joerg Henkel, Preeti Ranjan Panda, Sridevan Parameswaran, Loganath Ramachandran
The 16th International Conference on VLSI Design (VLSI Design '03), New Delhi, January 2003
Specification and Design of Multimillion Gate SOCs
Ramesh Chandra, Joerg Henkel, Preeti Ranjan Panda, Sridevan Parameswaran, and Loganath Ramachandran
IEEE/ACM International Conference on Computer Aided Design (ICCAD '02), San Jose, November 2002
Memory Optimizations in Embedded Systems
Preeti Ranjan Panda
Embedded Systems Design Workshop, IIT Delhi, January 2002
Embedded Memories in System Design: Technology, Application, Design and Tools
Doris Keitel-Shulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda, and Nikil Dutt
International Conference on VLSI Design (VLSI Design'01), Bangalore, January 2001

INVITED TALKS

Memory Architectures for Embedded Systems-on-Chip
Preeti Ranjan Panda and Nikil Dutt
9th International Conference on High Performance Computing (HiPC 2002), December 2002
SystemC - A modeling platform supporting multiple design abstractions
Preeti Ranjan Panda
International Symposium on System Synthesis (ISSS '01), Montreal, October 2001
Application Specific Memory Customization
Preeti Ranjan Panda
SSGRR International Conference on Advances in Computer Infrastructure, L'Aquila, Italy, July/August 2000