Publications

External Links: Google Scholar, DBLP

Books

Book Cover: Power-efficient System Design Power-efficient System Design
Preeti Ranjan Panda, Aviral Shrivastava, B. V. N. Silpa, Krishnaiah Gummidipudi
Springer, New York, 2010.
Book Cover: Memory Issues in Embedded Systems-On-Chip: Optimizations and
Exploration Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration
Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
Kluwer Academic Publishers, Norwell, 1999.

Book Chapters

  1. Memory Architectures, Preeti Ranjan Panda, in Handbook of Hardware/Software Codesign, Eds. Soonhoi Ha and Juergen Teich, Springer, 2017
  2. Energy-efficient Memory Port Assignment, Preeti Ranjan Panda and Lakshmikantam Chitturi, in Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach, Eds. Florin Balasa and Dhiraj Pradhan, Chapman & Hall/CRC Press, 2011
  3. Power Optimisation Strategies Targeting the Memory Subsystem, Preeti Ranjan Panda, in Designing Embedded Processors - A Low Power Perspective (eds. Jorg Henkel and Sri Parameswaran), Springer, pp131-155, 2007
  4. Memory Architectures for Embedded Systems-on-Chip, Preeti Ranjan Panda and Nikil Dutt, Lecture Notes in Computer Science (LNCS) Vol. 2552, Springer-Verlag, 2002, pp. 647-662
  5. Improving Cache Performance through Tiling and Data Alignment, Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau, Lecture Notes in Computer Science (LNCS) Vol. 1253, Springer-Verlag, 1997, pp. 167-185

Journal Papers

  1. R. Jain, P. R. Panda, and S. Subramoney, Cooperative Multi-Agent Reinforcement Learning based Co-optimization of Cores, Caches, and On-chip Network, ACM Transactions on Architecture and Code Optimization (TACO), accepted for publication, 2017.
  2. Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharyya, Deepak Chauhan, Sharad Kumar: Managing Trace Summaries to Minimize Stalls During Postsilicon Validation. IEEE Trans. VLSI Syst. (TVLSI) 25(6): 1881-1894 (2017)
  3. Prasenjit Chakraborty, Preeti Ranjan Panda, Sandeep Sen, Partitioning and Data Mapping in Reconfigurable Cache and Scratch Pad Memory based Architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), 22(1), 2016
  4. Iason Filippopoulos, Namita Sharma, Per Gunnar Kjeldsberg, Francky Catthoor, Preeti Ranjan Panda, Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures , ACM Transactions on Embedded Computing Systems (TECS), 15(3), 2016
  5. Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Min Li, Prashant Agrawal, Data Flow Transformation for Energy Efficient Implementation of Givens Rotation Based QRD , ACM Transactions on Embedded Computing Systems (TECS), 15(1), 2016
  6. Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda, Area-Aware Cache Update Trackers for Postsilicon Validation , IEEE Transactions on VLSI Systems(TVLSI), 24(5), 2016
  7. Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Praveen Raghavan, Tom Vander Aa, Array Interleaving - An Energy-Efficient Data Layout Transformation , ACM Transactions on Design Automation of Electronic Systems (TODAES), 20(3), 2015
  8. Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda, Shared-port register file architecture for low-energy VLIW processors , ACM Transactions on Architecture and Code Optimization (TACO) 11(1): 1 (2014)
  9. Exploiting UML based validation for compliance checking of TLM 2 based models, Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda, Design Autom. for Emb. Sys. (DAES) 16(2): 93-113 (2012)
  10. Compressing Cache State for Post-Silicon Processor Debug, Preeti Ranjan Panda, M. Balakrishnan, and Anant Vishnoi, IEEE Transactions on Computers (TC), 60(4): 484-497, 2011
  11. Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures, Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, and Anshul Kumar , International Journal of Parallel Programming (IJPP), Vol. 35, No. 6, pp507-527, 2007
  12. Memory Allocation and Mapping in High-level Synthesis: An Integrated Approach, Jaewon Seo, Taewhan Kim, and Preeti Ranjan Panda , IEEE Transactions on VLSI Systems (TVLSI), Vol. 11, No. 5, October 2003
  13. Data Memory Organization and Optimizations in Application-Specific Systems, P. R. Panda, N. D. Dutt, A. Nicolau, F. Catthoor, A. Vandecappelle, E. Brockmeyer, C. Kulkarni, and E. de Greef , IEEE Design and Test of Computers (D & T), Vol. 18, No. 3, May/June 2001.
  14. Data and memory optimization techniques for embedded systems, P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, and P. G. Kjeldsberg, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 6, No. 2, April 2001 (Most Downloaded ACM TODAES Paper)
  15. On chip vs. off chip memory: the data partitioning problem in embedded processor-based systems , Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau , ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 5, No. 3, July 2000 (Listed in Top 10 Downloaded ACM TODAES Papers)
  16. Low Power Memory Mapping through Reducing Address Bus Activity, Preeti Ranjan Panda and Nikil D. Dutt , IEEE Transactions on VLSI Systems (TVLSI), Vol. 7, No. 3, September 1999
  17. High-Level Synthesis with SDRAMs and RAMBUS DRAMs , Asheesh Khare, Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau , IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Vol. E82A, No. 11, pp 2347-2355, 1999
  18. Augmenting Loop Tiling with Data Alignment for Improved Cache Performance , Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau , IEEE Transactions on Computers (TC), Vol 48, No. 2, February 1999
  19. Local Memory Exploration and Optimization in Embedded Systems , Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 18, No. 1, January 1999.
  20. Incorporating DRAM Access Modes in High-Level Synthesis , Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 17, No. 2, February 1998
  21. Memory Data Organization for Improved Cache Performance in Embedded Processor Applications , Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau , ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 2, No. 4, October 1997
  22. Estimating the complexity of synthesized designs from FSM Specifications , Biswadip Mitra, Preeti Ranjan Panda, and P. Pal Chaudhary, IEEE Design & Test of Computers (D & T) , March 1993

Conference Papers

  1. Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi: Reusing trace buffers to enhance cache performance. Design Automation and Test in Europe (DATE), Lausanne, 2017: 572-577
  2. Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney: A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. Design Automation and Test in Europe (DATE), Lausanne, 2017: 800-80
  3. R. Jain, P. R. Panda, and S. Subramoney, Machine Learned Machines: Adaptive Co-optimization of Caches, Cores, and On-chip Network, Design Automation and Test in Europe (DATE), Dresden, March 2016 (Best Interactive Presentation Candidate)
  4. S. Chandran, P. R. Panda, S. R. Sarangi, D. Chauhan, and S. Kumar, Extending Trace History Through Tapered Summaries in Post-silicon Validation , Asia and South Pacific Design Automation Conference (ASP-DAC), Macau, January 2016 (Best Paper Candidate)
  5. S. Chandran, E. Peter, P. R. Panda, S. R. Sarangi, A Generic Implementation of Barriers using Optical Interconnects, Intl. Conference in VLSI Design and Embedded Systems (VLSI Design), Kolkata, January 2016
  6. Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Energy efficient FFT implementation through stage skipping and merging, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Amsterdam, October 2015
  7. Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma, Vaidyanathan Srinivasan, Dipankar Sarma, Power Optimization Techniques for DDR3 SDRAM , Intl. Conference in VLSI Design and Embedded Systems (VLSI Design), Bangalore, January 2015: 310-315
  8. Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan, Array scalarization in high level synthesis, Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, January 2014: 622-627
  9. Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan, Energy optimization in Android applications through wakelock placement , Design Automation and Test in Europe (DATE), 2014
  10. Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor, Energy efficient data flow transformation for Givens Rotation based QR Decomposition ,Design Automation and Test in Europe (DATE), 2014
  11. Preeti Ranjan Panda, Sourav Roy, Srikanth Chandrasekaran, Namita Sharma, Jasleen Kaur, Sarath Kumar Kandalam, Nagaraj N., High level energy modeling of controller logic in data caches , ACM Great Lakes Symposium on VLSI (GLS-VLSI), 2014, 45-50
  12. Prasenjit Chakraborty, Preeti Ranjan Panda, SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems , International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2013
  13. Namita Sharma, Tom Vander Aa, Prashant Agrawal, Praveen Raghavan, Preeti Ranjan Panda, and Francky Catthoor, Data memory optimizations in LTE downlink ,International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2013
  14. Space sensitive cache dumping for post-silicon validation
    Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda
    Design, Automation and Test in Europe (DATE'13) 2013: 497-502
  15. Power Supply Efficiency Aware Server Allocation in Data Centers
    Preeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan
    Intl. Conference on VLSI Design and Embedded Systems (VLSI Design'13), Pune, 2013: 233-238
  16. Integrating software caches with scratch pad memory
    Prasenjit Chakraborty, Preeti Ranjan Panda
    15th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'12) 2012, Tampere, Finland, pp 201-210
  17. Efficient on-line algorithm for maintaining k-cover of sparse bit-strings
    Amit Kumar, Preeti Ranjan Panda, Smruti R. Sarangi
    IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science (FSTTCS'12), Hyderabad, 2012, pp 249-256
  18. Exploiting temporal decoupling to accelerate trace-driven NoC emulation
    Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar
    9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'11), Taipei, Taiwan, 2011, pp 315-324
  19. A SysML Profile for Development and Early Validation of TLM 2.0 Models
    Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
    7th European Conference Modelling Foundations and Applications (ECMFA'11), Birmingham, UK, 2011, pp 299-311
  20. A UML based framework for efficient validation of TLM 2 models
    Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
    Forum on Specification & Design Languages, (FDL'11), Oldenburg, Germany, 2011, pp 1-8
  21. Enhancing post-silicon processor debug with incremental cache state dumping
    Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan
    18th IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC'10), Madrid, Spain, 27-29 September 2010, pp 55-60
  22. Front-End Design Flows for Systems on Chip: An Embedded Tutorial
    Anshul Kumar, Preeti Ranjan Panda
    Intl. Conference on VLSI Design and Embedded Systems (VLSI Design'10), pp 417-422
  23. FastFwd: An Efficient Hardware Acceleration Technique for Trace-driven Network-on-Chip Simulation
    Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, and Anshul Kumar
    (CODES+ISSS'10), Scottsdale, USA, October 2010
  24. Rank Based Dynamic Voltage and Frequency Scaling for Tiled Graphics Processors
    B. V. N. Silpa, Gummidipudi Krishnaiah, and Preeti Ranjan Panda
    (CODES+ISSS'10), Scottsdale, USA, October 2010 (Best Paper Candidate)
  25. Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine
    B. V. N. Silpa, Kumar S. S. Vemuri, and Preeti Ranjan Panda
    International Symposium on Visual Computing (ISVC'09 (1))(LNCS 5785), Las Vegas, USA, November 2009, pp 111-124
  26. Online Cache State Dumping for Processor Debug
    A. Vishnoi, Preeti Ranjan Panda, and M. Balakrishnan
    Design Automation Conference (DAC'09), San Francisco, USA, July 2009
  27. Cache Aware Compression for Processor Debug Support
    A. Vishnoi, Preeti Ranjan Panda, and M. Balakrishnan
    Design, Automation and Test in Europe (DATE'09), Nice, France, April 2009
  28. A Generic Platform for Estimation of Multi-threaded Program Performance on Heterogeneous Multiprocessor
    A. Sahu, M. Balakrishnan, and Preeti Ranjan Panda
    Design, Automation and Test in Europe (DATE'09), Nice, France, April 2009
  29. Texture Filter Memory: A Power-efficient and Scalable Texture Memory Architecture for Mobile Graphics Processors
    B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, and G. S. Visweswaran
    IEEE/ACM International Conference on Computer Aided Design (ICCAD '08), San Jose, November 2008
  30. Unified Modeling Abstraction for Fast Simulation and Emulation
    G. Krishnaiah, Preeti Ranjan Panda, Ashok Janannathan, Sreenivas Subramoney, and Anshul Kumar
    3rd Workshop on Architectural Research Prototyping (WARP'08), Beijing, China, June 2008
  31. REWIRED - Register Write Inhibition by Resource Dedication
    Pushkar Tripathi, Rohan Jain, Srikanth Kurra, and Preeti Ranjan Panda
    13th Asia and South Pacific Design Automation Conference (ASPDAC '08), Seoul, Korea, pp28-31, January 2008
  32. An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform
    Rahul Jain and Preeti Ranjan Panda
    Intl. Symposium on Circuits and Systems (ISCAS'07), New Orleans, May 2007
  33. The Impact of Loop Unrolling on Controller Delay in High Level Synthesis
    Srikanth Kurra, Neeraj K Singh and Preeti Ranjan Panda
    Design Automation and Test in Europe (DATE'07), Nice, France, April 2007
  34. Power Reduction in VLIW Processor with Compiler Driven Bypass Network
    Neeraj Goel, Anshul Kumar and Preeti Ranjan Panda
    Intl. Conference on VLSI Design and Embedded Systems (VLSI'07), Bangalore, Jan 2007
  35. Customization of Register File Banking Architecture for Low Power
    Rakesh Nalluri, Rohan Garg and Preeti Ranjan Panda
    Intl. Conference on VLSI Design and Embedded Systems (VLSI'07), Bangalore, Jan 2007
  36. Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
    Rahul Jain and Preeti Ranjan Panda
    Intl. Conference on VLSI Design and Embedded Systems (VLSI'07), Bangalore, Jan 2007
  37. Energy efficient application specific banked register files
    Rakesh Nalluri and Preeti Ranjan Panda
    10th IEEE VLSI Design and Test Symposium (VDAT '06), Goa, August 2006, pp56-65
  38. A power efficient architecture for 2-D Discrete Wavelet Transform
    Rahul Jain and Preeti Ranjan Panda
    10th IEEE VLSI Design and Test Symposium (VDAT '06), Goa, August 2006, pp121-129
  39. Rapid estimation of control delay from high-level specifications
    Gagan Raj Gupta, Madhur Gupta, and Preeti Ranjan Panda
    43rd Design Automation Conference (DAC '06), San Francisco, USA, July 2006, pp455-458
  40. Abridged Addressing: A Low Power Memory Addressing Strategy
    Preeti Ranjan Panda
    11th Asia and South Pacific Design Automation Conference (ASPDAC '06), Yokohama, Japan, January 2006, pp892-897
  41. A technique for predicting the effect of data cache associativity
    Viresh Kumar and Preeti Ranjan Panda
    9th IEEE VLSI Design and Test Symposium (VDAT '05), Bangalore, August 2005, pp259-268
  42. Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
    Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, and Anshul Kumar
    Design Automation and Test in Europe (DATE '05), Munich, March 2005, pp730-735
  43. Extracting Exact Finite State Machines from Behavioral SystemC Descriptions
    Vikram Singh Saun and Preeti Ranjan Panda
    18th International Conference on VLSI Design (VLSI Design '05), Kolkata, January 2005, pp280-285
  44. Memory Architectures for Embedded Systems-on-Chip (invited paper)
    Preeti Ranjan Panda and Nikil Dutt
    9th International Conference on High Performance Computing (HiPC 2002), December 2002
  45. An Energy-conscious Algorithm for Memory Port Allocation
    Preeti Ranjan Panda and Lakshmikantam Chitturi
    IEEE/ACM International Conference on Computer Aided Design  (ICCAD '02), San Jose, November 2002
  46. An Integrated Algorithm for Memory Allocation and Assignment in High-level Synthesis
    Jaewon Seo, Taewhan Kim, and Preeti Ranjan Panda
    39th Design Automation Conference (DAC '02), New Orleans, June 2002
  47. SystemC - A modeling platform supporting multiple design abstractions (invited paper)
    Preeti Ranjan Panda
    International Symposium on System Synthesis (ISSS '01), Montreal, October 2001
  48. Cache-efficient memory layout of aggregate data structures
    Preeti Ranjan Panda, Luc Semeria, and Giovanni de Micheli
    International Symposium on System Synthesis (ISSS '01), Montreal, October 2001
  49. Application Specific Memory Customization (invited paper)
    Preeti Ranjan Panda
    SSGRR International Conference on Advances in Computer Infrastructure, L'Aquila, Italy, July/August 2000
  50. Memory Bank Customization and Assignment in Behavioral Synthesis
    Preeti Ranjan Panda
    IEEE/ACM International Conference on Computer Aided Design  (ICCAD '99), San Jose, November 1999
  51. High-Level Synthesis with Synchronous and RAMBUS DRAMs
    Asheesh Khare, Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    The Eighth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'98), Sendai, Japan, October 1998
  52. Data Cache Sizing for Embedded Processor Applications
    Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    Design Automation and Test in Europe (DATE'98), Paris, February 1998, pp925-926
  53. Exploiting Off-Chip Memory Access Modes in High-Level Synthesis
    Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    IEEE/ACM International Conference on Computer Aided Design (ICCAD '97), San Jose, November 1997
  54. A Data Alignment Technique for Improving Cache Performance
    Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau
    International Conference on Computer Design (ICCD '97), Austin, October 1997
  55. Architectural Exploration and Optimization of Local Memory in Embedded Systems
    Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    International Symposium on System Synthesis (ISSS '97), Antwerp, September 1997
  56. Improving Cache Performance through Tiling and Data Alignment
    Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, and Alexandru Nicolau
    The 4th International Symposium on Solving Irregularly Structured Problems in Parallel (IRREGULAR'97), Paderborn, June 1997
  57. Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications
    Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    European Design and Test Conference (ED & TC '97), Paris, March 1997
  58. Behavioral Array Mapping into Multiport Memories Targeting Low Power
    Preeti Ranjan Panda and Nikil D. Dutt
    10th International Conference on VLSI Design (VLSI Design '97), Hyderabad, January 1997
  59. Memory Organization for Improved Data Cache Performance in Embedded Processors
    Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau
    International Symposium on System Synthesis (ISSS '96), La Jolla, November 1996
  60. Low Power Mapping of Behavioral Arrays to Multiple Memories
    Preeti Ranjan Panda and Nikil D. Dutt
    International Symposium on Low Power Electronics and Design (ISLPED '96), Monterey, August 1996
  61. Reducing Address Bus Transitions for Low Power Memory Mapping
    Preeti Ranjan Panda and Nikil D. Dutt
    European Design and Test Conference (ED & TC '96), Paris, March 1996
  62. 1995 High Level Synthesis Design Repository
    Preeti Ranjan Panda and Nikil D. Dutt
    International Symposium on System Synthesis (ISSS '95), Cannes, September 1995
  63. Fibre Channel Protocol: Formal Specification and Verification
    Vijay Nagasamy, Sreeranga Rajan, and Preeti Ranjan Panda
    Silicon Valley Networking Conference (SVNC '95), San Jose, April 1995
  64. Estimating the complexity of synthesized designs from FSM Specifications
    Biswadip Mitra, Preeti Ranjan Panda, and P. Pal Chaudhary
    5th International Conference on VLSI Design (VLSI Design '92), Bangalore, Jan 1992 (Honourable Mention Award)

  65. A Flexible Scheme for State Assignment Based on Characteristics of the FSM
    Biswadip Mitra, Preeti Ranjan Panda, and P. Pal Chaudhary
    International Conference on Computer Aided Design (ICCAD '91), Santa Clara, November 1991
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