Most Recent Publications

 

  1. P Panda, M Balakrishnan and A. Vishnoi, “Compressing Cache State for Post-Silicon Processor Debug”  IEEE Transactions on Computers, Vol. 60, No. 4, April 2011, pp 484-497 (scheduled for publication)

  2. R. Devadoss, K. Paul, M. Balakrishnan, “A Tiled Programmable Fabric using QCA”,  FPT 2010, Beijing, Dec. 2010, pp. 9-16

  3. Preeti Ranjan Panda, Anant Vishnoi and M. Balakrishnan, “Enhancing post-silicon processor debug with Incremental Cache state Dumping”, IEEE VLSI-SOC, Madrid, Spain, September 2010, pp. 55-60

  4. R. Devadoss, K. Paul, M. Balakrishnan,  Clocking-based Coplanar Wire Crossing Scheme for QCA at 23rd Proceedings of the International Conference on VLSI Design, Bengaluru, India, Jan. 2010, pp. 339-344

  5. R. Devadoss, K. Paul, M. Balakrishnan, “Coplanar QCA crossovers”, Electronics Letters, Volume 45,  Issue 24,  November 19 2009, pp.1234 – 1235

  6. Sonali Chouhan, Ranjan Bose, M. Balakrishnan, “Integrated Energy Analysis of Error Correcting Codes and Modulation for Energy Efficient Wireless Sensor Nodes”, IEEE Transactions on Wireless Communications, Volume 8,  Issue 10,  October 2009, pp. 5348 – 5355

  7. R. Devadoss, K. Paul, M. Balakrishnan, Clocking-based Coplanar Wire Crossing Scheme for QCA at 1st International Workshop on Quantum-dot Cellular Automata, UBC, Vancouver, Canada, Aug. 2009.

  8. Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan, “Online Cache State Dumping for Processor Debug”. DAC 2009, pp. 358-363, Aug. 2009

  9. Sonali Chouhan, M. Balakrishnan, Ranjan Bose, “An Experimental Validation of System Level Design Space Exploration Methodology for Energy Efficient Sensor Nodes”, ISLPED 2009,  pp. 355-358, Aug. 2009

  10. Sonali Chouhan, Ranjan Bose, M. Balakrishnan, “A Framework for Energy Consumption Based Design Space Exploration for Wireless Sensor Nodes”, IEEE TCAD, Volume 28,  Issue 7,  July 2009, pp. 1017 – 1024

  11. Anant Vishnoi, Preeti Ranjan Panda and  M. Balakrishnan,  “Cache Aware Compression for Processor Debug Support”   Design Automation and Test in Europe (DATE), 20-24 April, Nice, France, pp. 208-213, April 2009

  12. Sahu, M. Balakrishnan and Preeti Ranjan Panda, “A Generic Platform for Estimation of Multi-threaded Program Performance on Heterogeneous Multiprocessor”, Design Automation and Test in Europe (DATE) 20-24 April, Nice, France, pp. 1018-1023, April 2009

  13. Kolin Paul,  M. Balakrishnan, Advait Jain, Pulkit Gambhir and Priyanka Jindal, “FPGA Accelerator for Protein Structure Prediction Algorithms” SPL 2009, Sao Carlos, Brazil, 1-3 April 2009, pp. 123-128

  14. Sonali Chouhan, M. Balakrishnan and Ranjan Bose, A Framework for Energy Consumption Based Design Space Exploration for Wireless Sensor Nodes, In International Symposium on Low Power Electronics and Design (ISLPED), Bangalore, India, pp. 329-334, Aug 2008.

  15. Anup Gangwar, M. Balakrishnan, Anshul Kumar and Preeti Ranjan Panda, ``Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures'', International Journal of Parallel Programming (IJPP), Springer, The Netherlands, vol 35, pp. 507-527, Dec 2007

  16. M Balakrishnan, Kolin Paul, Ankush Garg, Rohan Paul, Dheeraj Mehra, Vaibhav Singh, P.V.M. Rao, Vishwas Goel, Debraj Chatterjee, Dipendra Manocha,  “Cane Mounted Knee-above Obstacle Detection and Warning System for the visually impaired”,  3rd ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications (MESA 2007), Las Vegas, Nevada, USA, September 2007

  17. Ashutosh Pal and M. Balakrishnan, ``A Behavioral Synthesis Approach to Distributed Memory FPGA Architectures'', FPL 2007, Amsterdam, 27- 29 Aug. 2007, pp. 517-520

  18. Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, M. Balakrishnan, Kolin Paul, Dipendra Manocha ,``Smart Cane for the Visually Impaired: Technological Solutions for Detecting Know above Obstacles and Accessing Public Buses'', Proc. of 11th International conference on Mobility and Transport for Elderly and Disabled Persons (TRANSED 2007), Montreal, Canada, June 2007

  19. Anup Gangwar, M. Balakrishnan and Anshul Kumar, ``Impact of Inter-cluster Mechanisms on ILP in Clustered VLIW Architectures'', ACM TODAES, Vol. 12, No. 1, Jan 2007, pp. 1-29. (Best Paper Award for ACM TODAES 2007)

  20. H. Dhand, Basant Dwivedi and M. Balakrishnan, ``New Approach to Architectural Synthesis: Incorporating QoS Constraint'', Proc. EMSOFT 2006, Seoul, Korea, Oct. 2006, pp.301-310.

  21. Basant K. Dwivedi, Arun Kejariwal, M. Balakrishnan and Anshul Kumar, ``Rapid Resource-Constrained Hardware Performance Estimation'', Proc. International Workshop on Rapid System Prototyping (RSP06), Chania, Crete, Greece, June 2006, pp 40-46.