Resume of M. Balakrishnan
Updated: 10th Aug 2015
Name: M. Balakrishnan
Date of birth:
Address for correspondence:
Postal address: Rm 117, CSE Department, SIT Building, IIT Delhi, New Delhi 110016
Telephone: 11-26591285 (office) 11-26863014 (res)
Facsimile: 11-26581060, 26592283
Field(s) of specialization:
Assistive devices for the visually impaired
Embedded system design
Behavioral and system level synthesis
System level design & modeling
Ph.D.(EE) 1984 IIT Delhi
(Thesis title : A Microprogram Generating system with Emphasis on Signal Processing Architectures)
B.E.(Hons.)(EEE) 1977 BITS,Pilani First rank in Engg. in 1977 (CGPA : 9.77)
Positions held, Date of joining and the Institution (In reverse chronological order):
Position Period Place
Coordinator, School of IT July ’15 – present ANSK School of IT, IIT Delhi
Deputy Director(Faculty) July ’09 – June’12 IIT Delhi
Dean(PGS&R) Sep. '06 – Aug. ‘09 IIT Delhi
Head Sep. '01 - Aug. '04 Dept. of CSE, IIT Delhi
Professor Aug. '97 – present Dept. of CSE, IIT Delhi
Visiting Prof. Aug '94 - Jul '95 LS Informatik XII, Univ. of Dortmund
Associate Prof. Apr '91 - July '97 Dept. of CSE, IIT Delhi
Assistant Prof. Dec '88 - Mar '91 Dept. of CSE, IIT Delhi
Visiting Scientist May '88 - Dec '88 Institut fuer Informatik, Univ. of Kiel
Assistant Prof. Sep '87 - May '88 Dept. of ECE, Syracuse Univ.
Research Associate Sep '85 - Aug '87 Dept. of CIS, Univ. of Guelph
Scientist May '77 - Aug '85 CARE, IIT Delhi
(SRA, SSO-II, SSO-I)
Awards and fellowships
Name of the body
Nature of the award
NCPEDP-Mphasis Universal Design
Vasvik Award 2005
Research that is industrially relevant
SIGDA (given at DAC 2007)
TODAES 2007 Best paper Award
Konrad Zuse fellow
NRDC invention award
Silver medal (I in Engg. 1977)
NCERT and IARI
NSTS Scholarship (Agri. Engg.) Not accepted
Birla Higher Secondary School
Professional Achievements and contributions:
· 23 journal, 84 refereed conference publications, one book chapter, six patents including two PCTs, one trademark and one design registration (List of publications in Annexures A, B, C and D)
· 28 sponsored research projects (Rs. 11.56 crores) with PI in 14 of them (Rs 6.57 crores) . Apart from that 21 consultancies including from leading EDA/VLSI companies (Annexure E)
· 10 PhDs and 3 MS(R) completed, 3 PhD thesis under assessment and 5 Ongoing PhDs (Annexure F)
· 100 M.Techs. and 73 B.Tech projects supervised
· Many significant contributions to technical activities and professional societies (Annexure G)
· Many key initiatives in VLSI/Embedded systems education as well as higher education in general (Annexure H)
Key Outside IIT Delhi Memberships and Roles:
· Educational Institutions
- Member, Academic Council, SMVDU, Jammu (2006 - 2014)
- Member, Advisory role of Indraprastha Institute of Information Technology (IIIT) Delhi (2008-)
- Alumni advisory committee, BITS Pilani, (2011 - 2014 )
- Member, Academic Council, JNU (2012 - 2015)
Board of Directors, KritiKal Solutions
- Director (Non-executive), TCIL (2009 - 2013)
- Director (Non-executive), ITI (2009 - 2013)
- Associate Editor, IEEE Embedded Systems Letters (ESL) (2013 - )
- Steering Committee Member, VLSI Design (2006 - )
- ACM DSP Committee, ACM New York (2011 – 2015)
- Member, Research Advisory Council, CEERI, Pilani (CSIR laboratory) (2010 - )
- Member, Industrial Applications Working Group, MCIT, Govt. of India (2010 - 2013 )
- Member, Microelectronics Working Group, MCIT, Govt. of India (2010 - 2013)
- Senior Member, IEEE
- Senior Member, ACM
- Founding Member, ACM India Council (2009- 2012)
- President, ACM NCR Chapter
Referees (detailed office/residence addresses or phone numbers on request):
Prof. Surendra Prasad, ex-Director, IIT Delhi, New Delhi, 110016
Prof. Anshul Kumar, Professor, CSE
Prof. S.N. Maheshwari, Professor, CSE
Prof. V.S. Ramamurthy, (Ex-Chairman, BoG, IIT Delhi), Emeritus Professor, NIAS, Bangalore
Dr. Sanjiv Narayan, Vice President, Calypto Design Systems, NOIDA
Mr. V.B. Taneja, Retired Senior
Prof. Sharad Malik, Chairman, Department of Electrical Engineering, Princeton University, USA
Prof. Vishwani Agrawal, Auburn University, USA
Prof. Peter Marwedel, Department of
Complete list of publications in standard refereed journals
1. Manish Kumar
Jaiswal, B. Sharat Chandra Verma, Hayden K.-H. So, M. Balakrishnan, Kolin Paul,
Ray C.C. Cheung, “Configurable
Architectures for Multi-Mode Floating Point Adders”, Accepted for publication in IEEE Trans. On
Circuits and Systems I
2. Arun Kumar Parakh, M. Balakrishnan and Kolin Paul, “Improving Map-Reduce for GPUs with cache”, Int. J. High Performance Systems Architecture, Vol. 5, No. 3, 2015, pp. 166-177
3. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, “Series Expansion based Efficient Architectures for Double Precision Floating Point Division”, Circuits Systems and Signal Processing, vol. 33, No. 11, 2014, pp. 3499-3526
4. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, “Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder”, IEEE Trans. on Circuits and Systems Vol. 61-II, No. 7, 2014, pp. 521-525
5. Gayathri Ananthanarayanan, Geetika Malhotra, M. Balakrishnan, and Smruti R. Sarangi, “Amdahl's Law in the Era of Process Variation”, Vol. 4, No. 4, 2013, International Journal of High Performance Systems Architecture (IJHPSA), pp. 218-230
6. Sonali Chouhan, M. Balakrishnan, Ranjan Bose, "System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation", IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 31, No.4, 2012, pp. 586-596
7. Rajeswari Devadoss, Kolin Paul, M. Balakrishnan, "p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata", JETC, Vol. 7, No. 3, 2011, Article No. 13
8. P Panda, M Balakrishnan and A. Vishnoi, “Compressing Cache State for Post-Silicon Processor Debug” IEEE Transactions on Computers, Vol. 60, No. 4, April 2011, pp 484-497
9. R. Devadoss, K. Paul, M. Balakrishnan, “Coplanar QCA crossovers”, Electronics Letters, Volume 45, Issue 24, November 19 2009, pp.1234 – 1235
10. Sonali Chouhan, Ranjan Bose, M. Balakrishnan, “Integrated Energy Analysis of Error Correcting Codes and Modulation for Energy Efficient Wireless Sensor Nodes”, IEEE Transactions on Wireless Communications, Volume 8, Issue 10, October 2009, pp. 5348 - 5355
11. Sonali Chouhan, Ranjan Bose, M. Balakrishnan, “A Framework for Energy Consumption Based Design Space Exploration for Wireless Sensor Nodes”, IEEE Trans. on CAD of Integrated Circuits and Systems, Volume 28, Issue 7, July 2009, pp. 1017 - 1024
12. Anup Gangwar, M. Balakrishnan, Anshul Kumar and Preeti Ranjan Panda, ``Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures'', International Journal of Parallel Programming (IJPP), Springer, The Netherlands, vol 35, pp. 507-527, Dec 2007
13. Anup Gangwar, M. Balakrishnan and Anshul Kumar, ``Impact of Inter-cluster Mechanisms on ILP in Clustered VLIW Architectures'', ACM TODAES, Vol. 12, No. 1, Jan 2007, pp. 1-29. (Best Paper Award for ACM TODAES 2007)
14. Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar, ``Efficient Technique for Exploring Register File SIze in ASIP Design'', IEEE Trans. on VLSI, vol. 23, No. 12, pp. 1693-1699, Dec. 2004.
15. L. Wehmeyer, Manoj Jain, Stefan Steinke, Peter Marwedel and M. Balakrishnan, "Analysis of the Influence of Register File Size on Energy Consumption, Code Size and Execution Time" IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 20, no. 11, Nov. 2001, pp. 1329-1337.
16. M. Balakrishnan and Heman Khanna, ``Allocation of FIFO Structures in RTL Data Paths", ACM TODAES, July 2000, pp. 294-310.
17. A.R. Naseer, M. Balakrishnan and Anshul Kumar, ``Direct Mapping of RTL Structures onto LUT based FPGAs'', IEEE Trans. on CAD of Integrated Circuits and Systems, Vol 17, No. 7, July 1998, pp. 624-631
18. Alok Mittal,Aditya Vailaya, S, Banerjee and M. Balakrishnan, "Real Time Vision System for Collision Detection" CSI Journal of Computer Science and Informatics, March 1995, pp. 13-29. (Best Paper Award of CSI Journal of Computer Science and Informatics 1995)
19. M.Balakrishnan, A.K.Majumdar, D.K.Banerji and J.G.Linders, "Synthesis of Decentralized Controllers from High Level Description", Euromicro Journal of Microprocessing and Microprogramming, Vol. 22, No. 3, May 1988, pp 217-229.
20. M.Balakrishnan, A.K.Majumdar, D.K.Banerji, J.G.Linders and J.C.Majithia, "Allocation of Multiport Memories in Data Path Synthesis", IEEE Trans. on CAD of Integrated Circuits and Systems, vol 7, April 1988, pp 536-540.
21. M.Balakrishnan, A.K.Majumdar, D.K.Banerji, J.G.Linders and J.C.Majithia, "A Semantic Approach to Modular Synthesis of VLSI Systems", Information Processing Letters, Vol 27, No. 1, Feb. 1988, pp 1-7.
22. M.Balakrishnan, B.B.Madan and P.C.P.Bhatt, "An Efficient Retargetable Micro-code Generating System", Euromicro Journal of Microprocessing and Microprogramming, Vol. 19, No. 4, Oct. 1987, pp 305-318.
23. M.Balakrishnan, P.C.P.Bhatt and B.B.Madan, "A Survey of Microprogramming Languages", Euromicro Journal of Microprocessing and Microprogramming, Vol. 17, No. 1, Jan. 1986, pp 19-27.
Complete list of papers published in peer reviewed conferences
1. Pulkit Sapra, Ankit Kumar Parsurampuria, Dhruv Gupta, Suman Muralikrishnan, Mayank Raj, Akash Anand, Vinit Darda, Rohan Paul, M Balakrishnan and P.V.M. Rao, “A Compliant Mechanism Design for Refreshable Braille Display Using Shape Memory Alloy”, Accepted for presentation at ASME – MESA 2015, 2-5 Aug 2015, Boston, USA
2. Dheeraj Mehra, Deepak Gupta, Vishwarath.T, Neil Shah, Piyush Chanana, Siddharth, Rohan Paul, BalaKrishnan M and PVM Rao, "Bus Identification System for Visually Impaired: Evaluation and learning from field trials", Presented at TRANSED 2015, 29-31 July 2015, Lisbon, Portugal
3. Rajeswari Devadoss, Kolin Paul and M Balakrishnan, “MajSynth : An n-input Majority Algebra based Logic Synthesis Tool for Quantum-dot Cellular Automata”, 22nd Intl. Workshop on Logic Synthesis, 12-13 June 2015, Mountain View, California
4. Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul, “Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform”, ARC 2015, 13-17 April, 2015, Bochum, Germany, pp. 373-382
6. Mrinal Mech, Kunal Kwatra, Supriya Das, Piyush Chanana, Rohan Paul, M. Balakrishnan, “Edutactile - A Tool for Rapid Generation of Accurate Guideline-Compliant Tactile Graphics for Science and Mathematics.”, ICCHP (2), 7-11 July, 2014, Paris, France, pp. 34-41
7. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul, “Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division”, ISVLSI 2014, 2-9 July 2014, Tampa, Florida, pp. 332-33
9. Smruti R. Sarangi, Gayathri Ananthanarayanan, and M. Balakrishnan, “LightSim : A Leakage Aware Ultrafast Temperature Simulator”, 19th ASP-DAC, 20-23 Jan 2014, Singapore, pp. 855-860
10. B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, "Accelerating Genome Assembly using Hard Embedded Blocks in FPGAs.", IEEE 27th International Conference on VLSI Design, 5-9 Jan 2014, Mumbai, pp. 306-311
11. Dhruv Jain, Akhil Jain, Rohan Paul, Akhila Komarika, M. Balakrishnan: A path-guided audio based indoor navigation system for persons with visual impairment, ASSETS '13, October 21-23 October, 2013, Bellevue, WA, USA, pp. 33.
12. Mansureh S, Kolin Paul and M Balakrishnan, "Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs" 20th Reconfigurable Architectures Workshop (RAW 2013), May 20-21, 2013, Boston, USA
14. Lava Bhargava, Ranjan Bose, M. Balakrishnan, “Novel Hardware Implementation of LLR-based Non-binary LDPC Decoders’, NCC 2013, New Delhi, Feb 2013
15. Arun Kumar Parakh, M. Balakrishnan, Kolin Paul, “Performance enhancement of Map-Reduce framework on GPU”, The 11th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN 2013), Feb 2013, Innsbruck, Austria
16. Dheeraj Mehra, M. Balakrishnan et.al., “Design for user testing of affordable bus identification and homing system for the visually impaired”, Presented at Transportation Research Board Annual Conference (TRB 2013), Washington D.C. USA, Jan 2013 (selected for presentation in a special session at TRB 2013 from TRANSED 2012), Proc. of 13th International conference on Mobility and Transport for Elderly and Disabled Persons (TRANSED 2012), Sep. 2012, New Delhi, India
17. Sharat Chandra Verma, Kolin Paul, M Balakrishnan, “Accelerating 3D-FFT using Hard Embedded Blocks in FPGA”, 23rd Proceedings of the International Conference on VLSI Design, Pune, India, Jan. 2013
18. Dhruv Jain, M. Balakrishnan et.al. “Design and user testing of an affordable cell phone based indoor navigation system for visually impaired”, Proc. of 13th International conference on Mobility and Transport for Elderly and Disabled Persons (TRANSED 2012), Sep. 2012, New Delhi, India, Best Paper Award (http://www.transed2012.in/Best%20Paper%20Awards/M__47)
19. Arun Kumar Parakh, M. Balakrishnan, Kolin Paul, “Performance estimation and application mapping on different GPUs”, 26th IEEE International Parallel & Distributed Processing Symposium Workshop (IPDPSW2012), May 2012, Shanghai, China
20. Rajeswari Devadoss, Kolin Paul, M. Balakrishnan, "Architecture and tools for programmable QCA", FPT 2011, Dec. 2011, Delhi, pp. 1-4
21. R. Devadoss, K. Paul, M. Balakrishnan, “A Tiled Programmable Fabric using QCA”, FPT 2010, Beijing, Dec. 2010, pp. 9-16
22. Preeti Ranjan Panda, Anant Vishnoi and M. Balakrishnan, “Enhancing post-silicon processor debug with Incremental Cache state Dumping”, IEEE VLSI-SOC, Madrid, Spain, September 2010, pp. 55-60
23. Rohan Paul, M. Balakrishnan et.al. "Smart Cane for the Visually Impaired" Proc. of 12th International conference on Mobility and Transport for Elderly and Disabled Persons, (TRANSED 2010), Hong Kong, June 2010 (Peter Chan Best Paper Award)
24. Vasudev Sharma, M. Balakrishnan et.al. “User Triggered Bus Identification and Homing System: Making Public Transport Accessible for the Visually Challenged”, Proc. of 12th International conference on Mobility and Transport for Elderly and Disabled Persons, (TRANSED 2010), Hong Kong, June 2010
25. R. Devadoss, K. Paul, M. Balakrishnan, Clocking-based Coplanar Wire Crossing Scheme for QCA at 23rd Proceedings of the International Conference on VLSI Design, Bengaluru, India, Jan. 2010, pp. 339-344
26. R. Devadoss, K. Paul, M. Balakrishnan, Clocking-based Coplanar Wire Crossing Scheme for QCA at 1st International Workshop on Quantum-dot Cellular Automata, UBC, Vancouver, Canada, Aug. 2009.
28. Sonali Chouhan, M. Balakrishnan, Ranjan Bose, “An Experimental Validation of System Level Design Space Exploration Methodology for Energy Efficient Sensor Nodes”, ISLPED 2009, pp. 355-358, Aug. 2009
29. Anant Vishnoi, Preeti Ranjan Panda and M. Balakrishnan, “Cache Aware Compression for Processor Debug Support” Design Automation and Test in Europe (DATE), 20-24 April, Nice, France, pp. 208-213, April 2009
30. Sahu, M. Balakrishnan and Preeti Ranjan Panda, “A Generic Platform for Estimation of Multi-threaded Program Performance on Heterogeneous Multiprocessor”, Design Automation and Test in Europe (DATE) 20-24 April, Nice, France, pp. 1018-1023, April 2009
31. Kolin Paul, M. Balakrishnan, Advait Jain, Pulkit Gambhir and Priyanka Jindal, “FPGA Accelerator for Protein Structure Prediction Algorithms” SPL 2009, Sao Carlos, Brazil, 1-3 April 2009, pp. 123-128
32. Sonali Chouhan,
M. Balakrishnan and Ranjan Bose, A Framework for Energy Consumption Based
Design Space Exploration for Wireless Sensor Nodes, In International Symposium
on Low Power Electronics and Design (ISLPED), Bangalore, India, pp. 329-334, Aug
33. M Balakrishnan,
Kolin Paul, Ankush Garg, Rohan Paul, Dheeraj Mehra, Vaibhav Singh, P.V.M. Rao, Vishwas
Goel, Debraj Chatterjee, Dipendra Manocha, “Cane Mounted Knee-above Obstacle Detection
and Warning System for the visually impaired”,
3rd ASME/IEEE International Conference on Mechatronic and Embedded
Systems and Applications (MESA 2007), Las Vegas, Nevada, USA, September 2007
34. Ashutosh Pal and M. Balakrishnan, ``A Behavioral Synthesis Approach to Distributed Memory FPGA Architectures'', FPL 2007, Amsterdam, 27- 29 Aug. 2007, pp. 517-520
35. Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, M. Balakrishnan, Kolin Paul, Dipendra Manocha ,``Smart Cane for the Visually Impaired: Technological Solutions for Detecting Know above Obstacles and Accessing Public Buses'', Proc. of 11th International conference on Mobility and Transport for Elderly and Disabled Persons (TRANSED 2007), Montreal, Canada, June 2007
36. H. Dhand, Basant Dwivedi and M. Balakrishnan, ``New Approach to Architectural Synthesis: Incorporating QoS Constraint'', Proc. EMSOFT 2006, Seoul, Korea, Oct. 2006, pp.301-310.
37. Basant K. Dwivedi, Arun Kejariwal, M. Balakrishnan and Anshul Kumar, ``Rapid Resource-Constrained Hardware Performance Estimation'', Proc. International Workshop on Rapid System Prototyping (RSP06), Chania, Crete, Greece, June 2006, pp 40-46.
38. Akhilesh Chaudhary, Gaurav Gupta and M Balakrishnan, ``Factoring Large Numbers Using FPGAs'', Proc of VLSI Design and Test Symposium (VDAT 2005), Bangalore, India, August 2005
39. Basant Kumar Dwivedi, Harsh Dhand, M.Balakrishnan and Anshul Kumar, ``RPNG: A Tool for Random Process Network Generation'', Proc of Asia and South Pacific International Conference in Embedded SoCs (ASPICES-2005), Bangalore, India, July 2005.
40. Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda and Anshul Kumar,``Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures'', Proc. of Design Automation and Test in Europe (DATE05), Munich, Germany, March 2005, pp. 730-735
41. Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, and Subhashis Banerjee, ``SMPS: An FPGA-based Prototyping Environment for Multiprocessor Embedded Systems'', IEEE/ACM Thirteenth International Symposium on Field Programmable Gate Arrays (FPGA-2005), Monterey, USA, February 2005
42. Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar, ``Integrated On-chip Storage Evaluation in ASIP Synthesis'', Proc. 18th International Conference on VLSI Design (VLSI-2005), Kolkata, India, January 2005, pp 274-279.
43. Gaurav Arora, Abhishek Sharma, M. Balakrishnan and D. Nagchoudhuri, ``ADOPT - An Approach to Activity Based Delay Optimization'', Proc. 18th International Conference on VLSI Design (VLSI-2005), Kolkata, India, January 2005, pp. 411-416.
44. Basant Kumar Dwivedi, Anshul Kumar and M.Balakrishnan, ``Automatic Synthesis of System on Chip Multiprocessor Architectures for Process Networks '', ISSS 2004, Sep. 8-10, 2004, Stockholm, Sweden, pp. 60-65.
45. Basant Kumar Dwivedi, Anshul Kumar and M.Balakrishnan, ``Synthesis of Application Specific Multiprocessor Architectures for Process Networks'', Proc. 17th International Conference on VLSI Design, January 2004, Mumbai, India, pp. 780-787.
46. Anup Gangwar, M. Balakrishnan and Anshul Kumar, ``Impact of Inter-cluster Communication Mechanisms on ILP in Clustered VLIW Architectures'', Proc. of the Workshop on Application Specific Processors (WASP-2, held in conjunction with MICRO-36), San Diego, USA, Dec. 2003, pp. 56-63.
47. Manoj Kumar Jain, M.Balakrishnan and Anshul Kumar, ``Exploring Storage Organization in ASIP Synthesis'', Euromicro Symposium on Digital System Design (Euro-DSD 2003), September 2003, Belek Near Antalya, Turkey, pp. 120-127.
48. Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant K. Dwivedi, M. Balakrishnan and Anshul Kumar "SoC Synthesis with Automatic Interface Generation", Proc. of 16th International Conference on VLSI Design (VLSI-2003), January 2003, New Delhi, India, pp. 585-590.
49. Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar, ``An Efficient Technique for Exploring Register File Size in ASIP Synthesis", Proc. of CASES 2002, Grenoble, France, Oct. 2002, pp. 252-261.
50. C.P. Joshi, Anshul Kumar and M. Balakrishnan, "A New Performance Evaluation Approach for System Level Design Space Exploration", Proc. of ISSS02, October 2002, Kyoto, Japan, pp. 180-185.
51. Bhuvan Middha, Varun Raj, Anup Gangwarm Anshul Kumar, M. Balakrishnan and Paolo Ienne, "A TRIMARAN Based Framework for Exploring the Design Space of VLIW ASIPS with Coarse Grain Functional Units", Proc. of ISSS02, October 2002, Kyoto, Japan, pp. 2-7.
52. Stefan Steinke, Nils Grunwald, Lars Wehmeyer, Rajeshwari Banakar, M. Balakrishnan and Peter Marwedel, "Dynamic copying of Instructions into Onchip Memory for Energy Reduction", Proc. of ISSS02, October 2002, Kyoto, Japan, pp. 213-218.
53. Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan and Peter Marwedel, "Scratchpad Memory: A Design Alternative for Cache On-chip Memory in Embedded Systems", Proc. of CODES 2002, Estes Park, Colorado, May 2002, pp. 73-78. (2nd most cited paper published in CODES/ISSS in 10 years; listed by Frank Vahid and Tony Givargis, “Highly Cited Ideas in System Codesign and Synthesis”, CODES+ISSS’08, October 19–24, 2008, Atlanta, Georgia, USA)
54. K.N. Murali Mohan, Rohini Krishnan, Anshul Kumar and M. Balakrishnan, " A New Divide and Conquer Method for Achieving High-speed Division in Hardware", Proc. of VLSI Design/ASPDAC 2002, Bangalore, India, Jan. 2002, pp. 535-540.
55. Vishal P. Bhatt, M. Balakrishnan and Anshul Kumar, `` Exploring the Number of Register Windows in ASIP Synthsis", Proc. of VLSI Design/ASPDAC 2002, Bangalore, India, Jan. 2002, pp. 233-238.
56. Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel and M. Balakrishnan, "Evaluating Register File Size in ASIP Design", Proc. of CODES 2001, Copenhagen, April 2001, pp. 109-114.
57. Basant K. Dwivedi, Jan Hoogerbrugge, Paul Stravers and M. Balakrishnan, "Exploring Design Space of Parallel Realizations: MPEG-2 Decoder Case Study", Proc. of CODES 2001, Copenhagen, April 2001, pp. 92-97.
58. Manoj Kumar Jain, M. Balakrishnan and Anshul Kumar, ``ASIP Design Methodologies: Survey and Issues", Proc. of the Intl. Conf. on VLSI Design, Bangalore, India, Jan. 2001, pp. 76-81.
59. Anupam Rastogi, M. Balakrishnan and Anshul Kumar, ``Integrating Communication Cost Estimation in Embedded Systems Design: A PCI Case Study", Proc. of the Intl. Conf. on VLSI Design, Bangalore, India, Jan. 2001, pp. 23-28.
60. Vivek Haldar, Gokul Varadhan, Abhishek Saxena, M. Balakrishnan and Subhashis Banerjee, ``Design of Embedded Systems for Real-Time Vision", Proc. Indian Conf. on Computer Vision, Graphics and Image Processing, (ICVGIP'2000), Bangalore, India, Dec. 2000.
61. Akshaye Sama, M. Balakrishnan and J.F.M. Theeuwen, ``Speeding up Power Estimation of Embedded Software", Proc. of ISLPED, 23-24th July 2000, Italy, pp. 191-196.
62. Arvind Rajawat, M. Balakrishnan and Anshul Kumar,``Interface Synthesis : Issues and Approaches", Proc. of 13th Intl. Conf. on VLSI Design, IEEE CS Press, Calcutta, India, Jan. 2000, pp.92-97
63. T. Vinod Kumar, P. Sharma, M. Balakrishnan and S. Malik, ``Processor Evaluation in an Embedded Systems Design Environment", Proc. of 13th Intl. Conf. on VLSI Design, IEEE CS Press, Calcutta, India, Jan. 2000, pp.98-103
64. Aviral Srivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar and M. Balakrishnan,``Optimal Hardware/Software Partitioning for Concurrent Specification using Dynamic Programming", Proc. of 13th Intl. Conf. on VLSI Design, IEEE CS Press, Calcutta, India, Jan. 2000, pp.110-113
65. Ajoy Chakravarthy and M. Balakrishnan,``Simulation and Modeling of a Multi-cast ATM Switch", Proc. of the 12th CSI/IEEE Intl. Conf. on VLSI Design, Goa, India, Jan. 1999, pp.242-247
66. Rashmi Goswami, V. Srinivasan and M. Balakrishnan, ``MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign", Proc. of 12th CSI/IEEE Intl. Conf. on VLSI Design, Goa, India, Jan. 1999, pp. 128-131
67. S.K. Lodha, Shashank Gupta, M. Balakrishnan and S. Banerjee,``Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign'',Proc. of 11th CSI/IEEE Intl. Conf. on VLSI Design, Chennai, India, Jan. 1998, pp. 97-102
68. Sitanshu Jain, M. Balakrishnan, Anshul Kumar and Shashi Kumar,``Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library'',Proc. of 11th CSI/IEEE Intl. Conf. on VLSI Design, Chennai, India, Jan. 1998, pp. 400-405
69. A.R. Naseer, M. Balakrishnan and Anshul Kumar, ``Optimal Clock Period for Synthesized Data Paths'', Proc. of 10th Intl. Conf. on VLSI Design, Hyderabad, India, Jan. 1997, pp. 134-139.
70. Gaurav Agarwal, Nitin Thapar, Kamal Agarwal, M. Balakrishnan and Shashi Kumar, ``A Novel Reconfigurable Co-processor Architecture'', Proc. of 10th Intl. Conf. on VLSI Design, Hyderabad, India, Jan. 1997, pp. 370-375
71. Heman Khanna and M. Balakrishnan, ``Allocation of FIFO Structures in RTL Data Paths'', Proc. of 10th Intl. Conf. on VLSI Design, Hyderabad, India, Jan. 1997, pp. 130-133.
72. A.R. Naseer, M. Balakrishnan and Anshul Kumar, ``A Novel Approach to Direct Realization of RTL Structures using FPGAs'', Proc. of Intl. Workshop on Logic and High Level Synthesis, Grenoble, France, December 1996
73. Alok Kumar, Anshul Kumar and M. Balakrishnan," Heuristic Search based Approach to Scheduling, Allocation and Binding in Data Path Synthesis", Proc. of 8th CSI/IEEE Intl. Conf. on VLSI Design, Delhi, India, Jan. 1995, pp. 75-80.
74. Varshneya, B.B. Madan and M. Balakrishnan," "Memory Coupled Scalable Multiprocessors" Proc. of the 1st Workshop on Parallel Processing, Bangalore, India, Dec. 1994, pp. 424-429.
75. A.R. Naseer, M. Balakrishnan and Anshul Kumar, "An Efficient Technique for Mapping RTL Structures onto FPGAs", Proc. FPL '94, Prague, Czech Republic, Sep. 1994, LNCS vol-849, pp. 89-110.
76. Varshneya, B.B. Madan and M. Balakrishnan," Concurrent Search and Insertion in K-Dimensional Height Balanced Trees", Proc. of Intl. Parallel Processing Symposium, Cancun, Mexico, May 1994, pp.883-887.
77. A.R.Naseer, M.Balakrishnan and Anshul Kumar, "A Technique for Synthesizing Data Part Using FPGAs ", Proc. of 2nd IEEE/ACM Intl. Symp. on FPGAs, Berkeley, California, Feb. 1994.
78. A.R.Naseer, M.Balakrishnan and Anshul Kumar, "FAST : FPGA Targeted RTL Structure Synthesis Technique", Proc. of 7th CSI/IEEE Intl. Conf. on VLSI Design, Calcutta, India, Jan. 1994, pp.21-24.
79. M.V. Rao, M. Balakrishnan and Anshul Kumar, "DESSERT: Design Space Exploration of RT Level Components", Proc. of 6th CSI/IEEE Intl. Conf. on VLSI Design, Bombay, India, Jan. 1993, pp. 299-304.
80. P.P. Nedungadi, M. Balakrishnan and Anshul Kumar, "Data Path Synthesis with Global Time Constraint",(Poster Paper) Proc. of 5th CSI/IEEE Intl. Conf. on VLSI Design, Bangalore, India, Jan. 1992, pp.322-323.
81. Alok Kumar, Anshul Kumar and M. Balakrishnan, " A Novel Integrated Scheduling and Allocation Algorithm for Data Path Synthesis", Proc. of VLSI Design '91, IEEE Computer Society Press, New Delhi, Jan. 1991, pp.212-218.
82. B.L. Priyadarshan, M. Balakrishnan, Anshul Kumar and G.S. Visweswaran, "SYMCAD : Synthesis of Microprogrammed Control for Automated VLSI Design", Proc. of Intl. Workshop of Microprogramming (MICRO-23), Orlando, Florida, Nov. 1990, pp. 176-182.
83. M.Balakrishnan and Anshul Kumar, "A Comparative Study of Techniques for Synthesis of Optimal Structures from Behavioral Descriptions", Proc. Of VLSI Design, Bangalore, India, Jan. 1990. (Reprinted in MicroArch, IEEE Technical Committee on Computer Architecture, Vol. 5, No. 1, April 1990, pp. 2-7.
84. M.Balakrishnan and P.Marwedel, "Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration", Proc. of 26th Design Automation Conference, '89, Las Vegas, Nevada, USA, June 1989 pp.68-74.
List of books or book chapters published
Anshul Kumar, M. Balakrishnan, Manoj Kumar Jain and Anup Gangwar, ``Customizing Embedded Processors for Specific Applications'', Recent Trends in Practice and Theory of Information Technology, Proc. of NRB Seminar, 10-11 January 2005, NPOL, Cochin, pp. 261-284, ISBN 81-309-0171-4, © DRDO, Publ. Viva Books Pvt. Ltd.
List of patents and other IPs filed
Following three patents have been filed
1. Multi-modal Infotainment Device, (1729/DEL/2014, 27th June 2015)
2. A Compliant Mechanism for Refreshable Braille Display Using Shape Memory Alloy (1575/DEL/2015 dated 5th June 2015 and PCT Application No. PCT/IN2015/050043 dated 8th June 2015)
3. A Split Grip Cane Handle Unit With Tactile Feedback For Directed Ranging (388/DEL/2014, 12th Feb. 2014)
4. A System for Generating Refreshable Tactile Text and Graphic (1669/DEL/2012, 31st May 2012 and PCT application No. PCT/IN2013/000347 dated 31st May 2013)
5. Cane-Mounted Waste Above Obstacle Detection & Warning System (1354/DEL/2007, 22nd June 2007)
6. User Triggered Bus Identification & Building Navigation System (1355/DEL/2007, 22nd June 2007)
Trademarks & Design Registrations
1. SmartCaneTM : A trademark registered on 18th Feb. 2014 for our Smart Cane device (application no.: 2680919)
2. Cane for Visually Impaired: Design registration on 21st Oct 2013 (application no.: 257665)
Sponsored Research and other significant professional activities
I have been involved in 28 sponsored projects with a total value of approximately Rs. 11.56 crores. I have been PI of 14 of these projects with a total value of approx 6.57 crores. Apart from DST, MCIT etc. I have carried out contract research for NRB, DRDO, Intel, Freescale and EADS
Currently ongoing and awarded projects include:
ICT Centre of Excellence on Tactile Graphics
DEITY, Govt. of India
Nov. 2014 –
INALSI: Indoor Navigarion with Access to Location Specific Information
May 2014 -
Smart Cane- Development Course for National and International dissemination
WELLCOME TRUST, UK
April 2014 –
Development of Open source screen reading software NVDA and enhancement with Indian Languages
Centre for Internet and Society, Bangalore
Feb. 2013 -
Affordable Refreshable Braille Displays based on Shape Memory Actuation
( Along with Saksham Trust,
Phoenix Medical, KritiKal Solutions)
WELLCOME TRUST, UK
(approx. 170 Lakhs
Apr. 2014 –
Development of a Low-cost Electronic Braille Display for the Visually Impaired
Sep. 2013 to Aug. 2015
OnBoard: Assistive Device for Public Bus Access for the Visually Impaired
Sep. 2013 to June 2015
Apart from these sponsored projects, I have undertaken 21 consultancies with the total approximate value of Rs. 117 lakhs. These include consulting to globally leading companies in EDA and VLSI like Synplicity, Sequence Design, ST Microelectronics etc. Other consultancy projects include embedded product development for Indian industry, Govt. bodies on system related issues and education related consultancies. Because of current preoccupation with projects for the visually impaired I do not undertake any consultancy projects currently.
PhD and Other Student Project Guidance
Ph.D. Currently registered:
*Rajesh Kedia, Ph.D. (2015- ), (
Topic: Design space exploration for mobility assistant for visually impaired (MAVI)
*Richa Gupta, Ph.D. (2015- )( Co-supervisor: P.V.M. Rao
Topic: Studies on perception of tactile diagrams by visually impaired
*Solomon Abera Bekele, Ph.D. (2014- ) ( Co-supervisor: Anshul Kumar
Topic: Multi-core power estimation and optimization
*Piyush Chanana, Ph.D. (2012- ) () Co-supervisor: PVM Rao
Topic: Mobility and navigation of Visually Impaired
*Gayathri Ananthanarayanan, Ph.D. (2011- ) () Co-supervisor: Smruti Sarangi
Topic: Power estimation for systems based on multi-core processors
Ph.D. – thesis reviews received/under evaluation/synopsis defense completed:
Synopsis presentation completed
*Arun Parekh, Ph.D. (2009- ) (Co-supervisor: Kolin Paul )
Topic: Performance Estimation and Mapping of Applications onto GPUs
* Rajeswari, Ph.D. (2008- )(firstname.lastname@example.org) Co-supervisor: Kolin Paul
Topic: Novel Architectures and Synthesis Methods for Quantum-dot Cellular Automata
Thesis reviews received
*Mansureh Shahraki, Ph.D. (2010- 2015) (email@example.com) Co-supervisor: Kolin Paul
Topic: Application Mapping onto Reconfigurable Coarse-Grained Arrays
*Sharat Chandra Varma, Ph.D. (2008- 2014) (firstname.lastname@example.org) Co-supervisor: Kolin Paul
Topic: Architecture Exploration of FPGA Based Accelerators for Bioinformatics Applications,
Current Affliation: Post-doctoral fellow, University of Hong Kong
* Lava Bhargava, Ph.D. (2005- 2013)(email@example.com) Co-supervisor: Ranjan Bose
Topic: Energy Estimation and Modeling of LDPC Decoders
Current affiliation: Associate Professor, NIT Jaipur
* Sonali Chauhan, Ph.D. 2010, (firstname.lastname@example.org) Co-supervisor: Ranjan Bose(EE)
Topic: An Integrated Framework for Energy Optimization of Wireless Sensor Nodes
Current Affliation: Assistant Professor, EE Deptt., IIT Gauhati
* Aryabartta Sahu, Ph.D., 2010, ) Co-supervisor: Preeti Ranjan Panda
Topic: Evaluation and Mapping of Applications on Heterogeneous Multiprocessor Systems
Current Affliation: Assistant Professor, CSE Deptt., IIT Gauhati
* Anup Gangwar, Ph.D. 2005, ( Co-supervisor: Anshul Kumar
Topic: Performance Driven Synthesis of Application Specific Clustered VLIW Processors
Current Affliation: eNVIDIA, Bangalore
* Basant Diwedi, Ph.D. 2005, ( Co-supervisor: Anshul Kumar
Topic: Synthesizing Application Specific Multiprocessor Architectures for Process Networks
Current Affliation: Synopsys, Bangalore
* Rajeshwari Banakar, Ph.D. 2003, () Co-supervisor: Ranjan Bose(EE)
Title: A Low Power Design Methodology for Turbo Encoder and Decoder
Current Affliation: Professor, & HoD, E&C Department, BVB Engineering College, Hubli
* Manoj Kr. Jain, Ph.D. 2003, () Co-supervisor: Anshul Kumar
Title: Exploring Register File Size and Memory Configuration in ASIP Synthesis
Current Affliation: Assistant Professor, Udaipur University, Udaipur
* A.R. Naseer, Ph.D. 1995, () Co-supervisor: Anshul Kumar
Title: Realization of Synthesized RTL Structures on LUT based FPGAs
Current Affliation: King Fahd University Of Petroleum And Minerals, Saudi Arabia
* Atul Varshneya, Ph.D. 1995, Co-supervisor: B.B. Madan
Title: Parallel Dictionary Operations: Algorithms and Architectures
Current Affliation: VP technology, Agnity, USA
Ph.D. Completed (Co-supervised their research though not a formal supervisor):
* Anant Vishnoi, Ph.D. (2003- )(email@example.com) Co-supervisor: Preeti Ranjan Panda
Topic: Cache Data Compression: Algorithms and Hardware Implementation
Current Affliation: GM Research, Bangalore
* Alok Kumar, Ph.D. 1993 (firstname.lastname@example.org) Supervisor: Anshul Kumar
Topic: A Versatile Data Path Synthesis Approach based on Heuristic Search
Current Affliation: CoWare Design
* C.P. Joshi, M.S. 2003, (email@example.com) Co-supervisor: Anshul Kumar
Title: Communication Modeling and Performance Analysis of Embedded Systems
* Piyush Gupta, M.S. 2003, (firstname.lastname@example.org) Co-supervisor: Sanjeev Kapoor
Title: Automating Functional Partitioning Over Heterogenenous Platforms for Design of Embedded Systems
* M. Anand, M.S. 1998, (email@example.com) Co-supervisor: Sanjiv Kapoor
Title: Hardware/Software Partitioning between Microprocessor and Reconfigurable Hardware
Apart from these supervised 100 M.Tech. and 73 B.Tech projects
Other Professional Activities
Member of ACM DSP, New York (selection of ACM Distinguished Speaker Awardees) (2011-2015)
Lectures at Philips Research, Philips Semiconductors, Wipro, Cadence Design Systems and numerous universities and research laboratories in Germany, France, The Netherlands, USA, Malaysia, Korea, Qatar and Singapore
Tutorials at two VLSI Design Conferences and two VDATs
Keynotes at more than twenty five conferences
Reviewer for IEEE TCAD, ACM TODAES and other journals
Technical Program Chair of VLSI Design 1995 and 2003
Organizing Chair FPT 2011, (Dec 2011)
TPC of VLSI, ISLPED, ASP-DAC, ED&TC, ISSS, CODES, DSD, ESTiMedia
Associate Editor, IEEE Embedded Systems Letters (ESL)(2013- )
Senior Member - IEEE, Senior Member - ACM
Chairman, Delhi-NCR ACM Chapter
Chairperson/Member of numerous PRS&G committees of DEITY, MCIT
Education: Key Initiatives and Contributions
VLSI-EDA-Embedded Systems/CS Domain
1. M.Tech. VDTT Programme: Key person in initiating the first fully industry sponsored M.Tech. programme in VLSI Design, Tools and Technology. Almost all the major VLSI and EDA companies have sponsored students to this programme at one time or other. This has emerged as an innovative nationally recognized post graduate programme attracting the very best students and setting a model of sponsorship as well as CS-EE successful collaboration.
2. Pioneered introduction of FPGAs in UG curriculum: Recognizing its potential early on i.e. in early 90’s, I have worked constantly towards introducing FPGAs in the UG curriculum. First it was in the form of project work and then it became part of the digital lab in mid-90s and today second year students in CS and EE go through a digital systems design experience around FPGAs. In this process developed an educational kit and transferred know-how to a micro-controller kit manufacturer for production; developed a set of experiments and conducted short workshops for teachers and 6-weel long workshop for students from other engineering colleges in eight summer vacations.
3. First Faculty-Student led Startup at IIT Delhi: IIT Delhi had an incubator with few takers from the Institute community. With the CS graduates of 2002, facilitated the first joint faculty-student led startup named ”KritiKal Solutions Pvt. Ltd.” (www.kritikalsolutions.com). KritiKal emerged as a trend setter motivating more than 25 such startups in the campus in the last 10 years. Kritikal Solutions acts as a design house in the area of Embedded Systems and Computer Vision and employs around 35 people now. It also has a subsidiary named KritiKal Secure Scan which has camera based security products. I remain a founder of KritiKal Solutions and spent half of my sabbatical time in 2004-2005 working with the startup; a trend which has been followed by a number of faculty members since in IIT Delhi.
4. Establishing the best known Embedded Systems Research Group in India: IIT Delhi has the strongest embedded systems research group with five faculty members and nearly twenty research students. This has been possible with myself working closely with Prof Anshul Kumar for over two decades. Today the group has more than five crores in research funding from Govt. as well as R&D units of industry in India and abroad. The group started regular workshops in system level design which has now emerged as one track in the VLSI design conference as Embedded Systems Conference.
5. ASSISTECH: A centre for technology solutions for the visually impaired: Established a centre that is dedicated to development of technology solutions for the mobility and education of the visually impaired. Initial success has been achieved with “Smart Cane” which today a commercial product is impacting the lives of thousands of visually impaired in India. Device is available under the ADIP scheme of Ministry of Scial Justice & Empowerment to those who cannot afford to buy it. With successful large scale trails of OnBoard - a User Triggered Bus Identification System in BEST buses in Mumbai, the device is ready for technology transfer. The affordable technology that we have created for production of high-quality tactile diagrams first time in India is already helping organizations like NCERT. This activity is sponsored by DEITY, Govt of India. Another promising work where a concept demonstrator has been built is a ‘Braille Tutor”. A key aspect of ASSISTECH that I am proud of is our success (jointly with Prof. P V M Rao of Mech. Engg.) in creating a truly inter-disciplinary group of students and research staff, an excellent network with user organizations and manufacturing industries to complete an eco-system of innovation followed by R&D and productization. Visit assistech.cse.iitd.ac.in for details.
6. Key Member of VLSI Design Conference: VLSI design conference has emerged as a key event attracting technical papers from India and abroad, a vibrant exhibition and a major networking event with 600 to 1000 delegates in each edition. In the last twenty years, I have continuously worked to promote the event and participated in many capacities. I have been the technical programme chair twice, proposed and initiated the design contest, been fellowship chair etc. Currently a member of the steering committee and participate actively in giving direction to the event.
7. Founding member of ACM India: In 2010,
started the ACM India section along with seven other founding members. It is
already growing and making an impact on technical activities in CS in India. Initiated
a unique event for CS PhD students in India to give national and international
visibility to CS research in India.
Beyond VLSI-EDA-Embedded Systems/CS Domain
8. Contributing to Enhancing the Research Profile of IIT Delhi: IITs have established an image world wide of a quality undergraduate institution. This is in spite of the fact that the graduate and doctoral students constitute 2/3rd of the student population – far surpassing most research universities, As Dean of Post Graduate Studies & Research, I initiated many programmes and activities that were geared towards increasing the number and quality of doctoral students and also projecting the Institute beyond its undergraduate education. The number of PhD students between 2006 and 2009 increased from approximately 780 to nearly 1350. Some significant initiatives are listed below.
a. Significant policy changes piloted include facilitating enrolment of project staff in masters and PhD programmes, easy changeover from masters to PhD and provision of admission of our UG students to PG programmes with advance standing.
b. On projecting the Institute research, an Open House on the fourth Saturday of April for public demonstration of research projects, a PG website listing major achievements of our PG students (www.iitd.ac.in/pg), international conference participation as well as thesis presentations Institute wide. Working with industry sponsors as well as alumni donors for strengthening the PG programmes and give it higher visibility. As part of this initiative, started celebration of National Science day (28th Feb.) as a research Scholars day where selected PhD students from different departments, present their work in a poster session as well as seminars.
c. Towards the same end with a view to creating a unique space for IIT Delhi among the NCR (National Capital Region) industries, a professional candidate registration scheme which permits engineers from industries to register for regular courses in the Institute to upgrade their knowledge and skills has been started. The programme attracts 50 to 100 candidates each semester.
9. Scaling up Research and Quality Education: There has been a major expansion of technical education but most of the faculty joining these new Institutions though expected to do PhD for career growth but have no exposure to quality research. With a view to address this, took initiative to introduce the summer faculty research fellowship programme that enables teachers from different colleges to spend time in summer associated with the faculty in the domain of their research interest. Started in summer of 2008, at present IIT Delhi hosts nearly 150 faculty members each year and a significant fraction of them start their research at IIT Delhi or elsewhere soon after that
10. Innovative Experiments in Education/Research: In the forefront of a majority of innovative changes that have happened in IIT Delhi in the last 15 years. This includes dual degree programme, 1-credit module research courses, member of the UG curriculum committee that was adopted in 2003, formalizing teaching assistantship functions etc. two major initiatives I would like to mention are as follows.
a. A distance education programme across continents (with Ethiopia) has been started at the post-graduate level. This was the outcome of a delegation I took to Ethiopia on the invitation of their education ministry. The programme envisaged instruction through 2-way audio-video links and a limited one-week interaction period per semester. Till date 8 programmes from four different disciplines have been completed. Nearly 450 Ethiopian Engg teachers (that constitute a majority of teachers in Ethiopia) have now been trained by IIT Delhi and more than 75 visits involving nearly 50 faculty members have been made. One direct consequence of this effort is that today, IIT Delhi is receiving large number of PhD candidates from Ethiopia – in fact the largest foreign student group in the campus. This effort is perhaps one of the largest post graduate distance education programmes in the world.
b. On the request of MHRD and invitation of Govt. of Mauritius, I lead a delegation of 6 faculty members to Mauritius for a feasibility study on setting up an IIT like Institution. The study produced a unique model of a research based academy transforming in 5 years to an IIT like Institution supporting both UG education and research. As a follow-up, the Mauritius Govt. through Mauritian research council prepared an implementation document for setting up an IITRA (International Institute of Technology Research Academy) – fully funded by the Mauritius Govt. and mentored by IIT Delhi in Mauritius. Though the programme has run into some implementation issues but the activity had the potential of bringing unique visibility to IIT Delhi’s research capability especially in Africa. Further, it could have emerged as a model for building new quality Institution in disciplines where availability of research qualified faculty is limited.