Awards

• 2005 VASVIK Award (Electrical & Electronic Sciences & Technology) shared with PV Madhusudhan Rao, M Balakrishnan and Dipendra Manocha.

Patents

• Smart Cane -- This is a device for helping visually challenged persons to navigate independently. Status: Provisional patent granted}
• Bus Identification Module -- This is a two way system which helps a visually challenged person to identify, orient and board a (public transport) bus. The solution is also customizable to build navigational aids for such persons inside buildings. Status: Provisional patent granted}
• Methods and applications for altitude measurement and fusion of time domain user context detection algorithm with floor detection and elevator/staircase motion recognition Status: Disclosure filed in US}
• Methods and Applications for User Context Detection for Personal navigation system on Mobile Handsets Status: Disclosure filed in US}

Publication

Refereed Journal Publications

• R. Devadoss, K. Paul, and M. Balakrishnan. Coplanar QCA crossovers. Electron. Lett. 45, 1234 (2009)
• K. Paul, D. R. Chowdhury, and P. P. Chaudhuri, ``Theory of Extended Linear Machines", IEEE Transactions on Computers, September 2002.

Refereed Conference Publications

• Kolin Paul and Tapas Kundu. Android on Mobile Devices: An Energy Perspective. vInternational Symposium on Advanced Topics on Embedded Systems and Applications. Bradford, UK, 29 June - 1 July, 2010 (Accepted)
• Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, M. Balakrishnan, Kolin Paul, Dipendra Manocha. Smart Cane for the Visually Impaired: Design, Implementation and Field Tesing of an affordable Obstacle Detection System. TRANSED 2010 (Best Paper).
• Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, M. Balakrishnan, Kolin Paul, Dipendra Manocha. User Triggered Bus Identification and Homing System: Making public transport accessible for the Visually Challenged. TRANSED 2010.
• Nagaraju P, P Brisk, P Ienne, A Kumar and Kolin Paul. A High-Level Synthesis Flow for Custom Instruction Set Extensions for Application-Specific Processors. ASPDAC 2010.
• Rajeswari D, Kolin Paul, M Balakrishnan.Clocking-based Coplanar Wire Crossing Scheme for QCA. VLSID 2010.
• M. Chowdhary, M. Chansarkar, M. Sharma, A. Kumar, K. Paul, M. Jain, C. Agarwal and G. Narula. Reliable Context Detection for Improving Positioning Performance and Enhancing user Experience. ION GNSS 2009 Conference
• Rajeswari D, Kolin Paul and M Balakrishnan. Clocking-based Coplanar Wire Crossing Scheme for QCA. International Workshop on Quantum-Dot Cellular Automata 2009
• A Jain and P Gambhir and P Gupta and M Balakrishnan and K. Paul, "FPGA Accelerator for Protein Structure Prediction Algorithms" SPL 2009.
• Nagaraju P, Anshul Kumar and Kolin Paul. A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions. VLSID 2008. Hyderabad January, 2008.
• Nagaraju P, Anshul Kumar and Kolin Paul. Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors VLSID 2008. Hyderabad January, 2008.
• Neeraj Goel and Kolin Paul. Hardware Controlled and Software Independent Fault Tolerant FPGA Architecture ADCOM 2007 Guwahati.
• Kolin Paul Joel Porquet. Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration. EUROMICRO Conference of Digital Systems Design 2007. August 27-31 2007. Lubeck Germany.
• M. Balakrishnan, Kolin Paul, Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, Dipendra Manocha. PVM Rao, V Singh, V Goel, D Mukherjee. Cane Mounted Knee Above Obstacle Detection and Warning System for the Visually Impaired. 3$^{rd}$ ASME/IEEE Conference on Mechatronics and Embedded Systems and Applications ASME-DETC 2007. September 4-7 2007, Las Vegas.
• Nagaraju Pothineni Anshul Kumar Kolin Paul. Recurring Pattern Identification and its Application to Instruction Set Extension. The 2007 International Conference on Computer Design (CDES'07) Las Vegas, Nevada, USA (June 25-28) 2007.
• Rohan Paul, Ankush Garg, Vaibhav Singh, Dheeraj Mehra, M. Balakrishnan, Kolin Paul, Dipendra Manocha. `Smart' Cane for the Visually Impaired:Technological Solutions for Detecting Waist-above Obstacles. TRANSED 2007 Montreal Canada June 2007
• Nagaraju Pothineni Anshul Kumar Kolin Paul. Application Specific Datapath Extension with Distributed I/O Functional Units. VLSID 2007. Bangalore January, 2007.
• Kolin Paul M Balakrishnan. Experiences of a Summer Workshop in Embedded Systems. Workshop on Embedded System Education, EMSOFT, South Korea . October, 2006.
• Nilesh Padhariya, Kolin Paul and Dheeraj Bhardwaj. A FLOPS Based Model for Performance Analysis and Scheduling of Applications for Single and Multiple CPUs. ICPP Workshops 2006.
• Neeraj Goel and Kolin Paul. Fault Tolerant FPGA using Redundant Columns. Proc of VLSI Design and Test Symposium(VDAT 2006), Goa, India.. July, 2006.
• Rahul Jain, Anindita Mukherjee and Kolin Paul. Defect-Aware Design Paradigm for Reconfigurable Architectures. IEEE Computer Society Annual IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006). April, 2006.
• Kolin Paul and Sanjay Rajopadhye. Back Propagation Algorithm: Achieving 5 GOPS on the Virtex-E. Book Chapter in FPGA Implementations of Neural Networks By Amos R. Omondi; Jagath C. Rajapakse (Eds.). 0-387-28485-0 March, 2006.
• H. Dhand, and N.Goel and M.Agarwal. H. Dhand, N.Goel, M.Agarwal and K.Paul, IIT Delhi Partial and Dynamic Reconfiguration in Xilinx FPGAs A Quantitative Study. VDAT 2005. August, 2005.
• Sanjay Rajopadhye and Kolin Paul . A 1.5-D Architecture for Back Propagation Training . Engineering Of Reconfigurable Systems and Algorithms (ERSA'05) . June, 2005.
• Clare Hugget and Koushik Maharatna and Kolin Paul. On the Implementation of 128-bit FFT/IFFT for High Performance WPAN. IEEE International Symposium on Circuits and Systems. May, 2005.
• Kolin Paul. An FPGA based Test Bed for Bio Inspired Computation. 12th Reconfigurable Architectures Workshop RAW 2005, Denver. April, 2005.
• K Paul and S Rajopadhye , ``A New Hardware/FPGA Implementation of the Back Propagation Algorithm" IEEE Annual Symposium on VLSI 2003
• P. P. Chaudhuri, B. Sikdar, and K. Paul, ``Tutorial on Theory and Application of Cellular Automata CA for VLSI Design and Test", in VLSID'00 INDIA, January 2000.
• K. Paul, D. R. Chowdhury, and P. P. Chaudhuri, ``Scalable Pipelined Micro-Architecture for Wavelet Transform", in Proc. of VLSID'00, INDIA, January 2000.
• K. Paul and D. R. Chowdhury, ``Application of GF($2^p$) CA in Burst Error Correcting Codes", in Proc. of VLSID'00, INDIA, January 2000.
• K. Paul, S. P. Chaudhuri, R. Ghosal, B. Sikdar, and D. R. Chowdhury, ``GF($2^p$) CA Based Vector Quantization for Fast Encoding of Still Images", in Proc. of VLSID'00 INDIA, January 2000.
• B. Sikdar, K. Paul, G. P. Biswas, C. Yang, V. Bopanna, S. Mukherjee, and P. P. Chaudhuri, ``Theory and Application of GF($2^p$) Cellular Automata as On-Chip Test Pattern Generator", in Proc. of VLSI'00 INDIA, January 2000.
• K. Paul, D. R. Chowdhury, and P. P. Chaudhuri, ``Cellular Automata Based Transform Coding for Image Compression", in Proc. of HiPC'99 INDIA, December 1999.
• K. Paul, P. Dutta, D. R. Chowdhury, P. K. Nandi, and P. P. Chaudhuri, ``A VLSI Architecture for On-Line Image Decompression using GF($2^p$) Cellular Automata", in Proc. of VLSID'99 INDIA, January 1999.
• K. Paul, A. Roy, P. K. Nandi, B. N. Roy, M. D. Purkhayastha, S. Chattopadhyay, and P. P. Chaudhuri, ``Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis", in Proc. of ATS'97 Singapore, December 1997.
• K. Paul, D. R. Chowdhury, and P. P. Chaudhuri, ``A Parallel Architecture for Generation of Fractals", in Proc. of ADCOM'97 INDIA, January 1997.

Invited Tutorials

• Kolin Paul "Multicores : Architectures, Programming and Beyond". ADCOMP 2007.

Communicated:

• L Bansal and M Balakrishnan and K. Paul "A Methodology for the design of Digital Processor for SHWS", submitted to The Journal of Signal Processing Systems (2008).