About Me

firefox-gray I am a Ph.D. scholar in the Computer Science and Engineering department at IIT Delhi. I joined in January 2015. I have finished my coursework requirements and passed my comprehensive examination in July 2016.
I am now delving into my research. My research area is Design Space Exploration for Embedded Systems. You can find more information about my research work here.

My research supervisors are Prof. M.Balakrishnan and Prof. Kolin Paul.

I am a recipient of Visvesvaraya Ph.D. fellowship supported by MeitY (Ministry of Electronics and Information Technology, Government of India).


Current CGPA = 9.74/10.0

Coursework at IITD:

Course Name Instructor Session
Theory of Computation Naveen Garg Spring, 2016-17
Low Power Computing Sorav Bansal Fall, 2016-17
Intelligent Information Processing Multiple Instructors Spring, 2015-16
System Level Design and Modeling M. Balakrishnan Fall, 2015-16
Advanced Data Structures S. N. Maheswari Fall, 2015-16
Compiler Optimizations Preeti R. Panda Fall, 2015-16
Communication Skills Akash Raha Fall, 2015-16
Operating Systems Sorav Bansal Spring, 2014-15
Architecture of High Performance Computers Anshul Kumar Spring, 2014-15
Embedded Computing Kolin Paul Spring, 2014-15
Low Power System Design Techniques M. Balakrishnan Spring, 2014-15

Course projects:

  1. Compiler Optimizations: Effective Last Level Cache (LLC) partitioning using static dynamic analysis (Use of compiler hints to aid cache partitioning for run time system).
  2. System Level Design and Modeling: Power Performance tradeoff analysis for High level synthesis of Matrix multiplier. [slides]
  3. Low Power Computing: Analysis and comparison of performance, power and energy for various workloads on different class of systems (laptop, desktop and server) using hardware counters. [Report]
  4. Advanced Data Structures: Implementation of Fibonacci heap and using it to implement Fredman Tarjan MST algorithm. Analysis and comparison of performance with standard Prim's algorithm. [Design doc] [Report]
  5. Architecture of High Performance Computers: Implementation of Tomasulo's out-of-order pipeline (with ROB) in an in-house architecture simulator (Tejas).
  6. Embedded Computing: Interfacing various sensors (Accel, Gyro, motion and proximity) to Intel Galileo board.
  7. Intelligent Information Processing: Analysis of Back Propagation Neural Network accuracy (by varying different parameters) for classification of Iris flowers. [Report]

Academics prior to IITD:

Degree Details Year Score
B.Tech. In ECE MNIT Jaipur 2002-2006 9.71/10
XII CHSE Orissa 2000-2002 83%
X CBSE 2000 89%


Research summary

I am working on Design space exploration for embedded systems. Design space exploration is a complex process involving filtering design choices of interest from exponentially large design options. My research focuses on tradeoffs between application level parameters and how to efficiently analyze them.

I will be using MAVI as a case study for my research.

An informal summary of the problem statement can be found at this link

Will add more details about the research in upcoming days.


  1. Rajesh Kedia, Yoosuf K K, Pappireddy Dedeepya, Munib Fazal, Chetan Arora, and M. Balakrishnan. "MAVI: An embedded device to assist mobility of visually impaired". In 30th International Conference on VLSI Design (VLSID), Jan. 2017. [Link to paper]

Open source releases

  1. Visualization tool: This is a generic visualization tool to plot graphs for data present in csv format and can be used by researchers to plot various kind of graphs to be included in reports/presentations/documents. Specific to my research, we have included some capabilities needed for efficiently performing Design Space Exploration. [Link to repository]

Suggested reading

This list contains selected research papers that I found worth sharing. [link]


Mobility Assistant for Visually Impaired

MAVI home page

Work Experience

Teaching Assistant (TA) Duties at IITD:

Course Name Instructor Session
Embedded Systems Design (ongoing) M. Balakrishnan Spring, 2017-18
Digital Logic and System Design Anshul Kumar Fall, 2017-18
Computer Architecture Anshul Kumar Spring, 2016-17
Embedded Computing Kolin Paul Fall, 2016-17
Operating Systems Kolin Paul Spring, 2015-16
System Level Design and Modeling M. Balakrishnan Fall, 2015-16
Big Data and Cloud Computing Karuna P. Joshi Spring, 2014-15

Key contributions during TA work:

  1. My primary contributions during TA work has been significant involvement in definition of lab exercises (System level design and modeling, Operating systems, Embedded computing, Computer architecture, and Digital logic and system design).
  2. Another important contribution is towards defining and implementing automated evaluation system using Moodle VPL. We have deployed this infrastructure for automated evaluation for courses (Operating systems, VHDL based digital system design) where automation was deemed very difficult. Overall, it has led to easing work for TAs and bring in uniformity, while improving students' experience of assignment submission.
  3. In all my TA work, the focus has been on methods to ensure objectivity of evaluation, and provide timely feedback to the students.
  4. Recommended as "Outstanding TA" 3 times and honourable mention once during 3 years.

Industry Experience:

Organization Period Summary of work
Texas Instruments India Pvt. Ltd. Jul 2006 - Dec 2014 Worked as a part of Microcontroller (MCU) design team: Design for Test (DfT), Functional Verification, Architecture Definition.

Other responsibilities at work

  1. Ph.D. student representative for CSE department (from Nov. 2016 till July 2017): coordinating events, communicate general concerns to higher authorities, areas to enable better experience for Ph.D. students, etc. Some notable contributions of the team are:
    • Organized annual PhD Symposium of IITD CSE/SIT departments in Dec. 2016.
    • Website rollout dedicated to our Ph.D. program.
    • Moving to a moodle based online entrance test from a paper based test - enabling a better experience for candidates and faculty in the admission process.
    • Conceptualized and enabled walk-in option for Ph.D. entrance test - providing opportunity to candidates who missed the application deadline.
  2. Member of the FUNACE team at TI for 2 years: coordinating fun events within the team, plan and enable better team building, etc.

Others/ External Links

My dblp profile

My LinkedIn Page

My facebook page

SMDP Workshop Dec 2015

Technical explorations

Preparing for Ph.D. interviews

My early foreign travel experiences

Some random writings

My wiki article on Bus Encoding

My wiki article on DSE

Contact Details

Email: kedia@cse.iitd.ac.in

Room 301, Research Scholar Room-A,
SIT Building, IIT Delhi,
Hauz Khas, New Delhi - 110016.


Template borrowed from Styleshout

Image Gallery

Giving demo of MAVI at VLSID 2018
With Prof. Vineet Sahula at VLSID 2018, met him after many years
At a tutorial on Assistive technologies by Prof. M. Balakrishnan at VLSID 2018
Attending VLSID 2017 in Hyderabad with Lokesh
Presenting MAVI paper in VLSID 2017
With Prof. Virendra Singh at VLSID 2017