Research Interests

My main research interest lies in the field of Analysis and Design of Algorithms. Currently, I am working on Approximation Algorithms for k-median facility location problem with outliers for my undergraduate thesis. During my undergraduate studies, I mainly explored Computer Architecture and Distributed Systems.

I have been involved in the following projects:

Undergraduate Thesis


  • Internship at IBM Research, Delhi: Co-operative De-Centralized Cache

    The objective of this work was to introduce consistency across caches for striping based distributed storage applications by reducing the number of objects which are partially present in the caches across all storage nodes. This would reduce the access time of an object and hence, enhance user experience

    We implemented our own cache on the top of a virtual file system and developed an enhanced caching technique wherein local cache events are asynchronously communicated to peer nodes to leverage correlation between data across different storage nodes.


  • Approximate Arithmetic Circuits

    This work aimed at developing approximate arithmetic circuits for use in high performance and energy efficient systems where a limited amount of error can be tolerated like image and video processing applications under Prof. Anshul Kumar.

    We designed an approximate and fast Wallace tree multiplier with 1-reduction layer by replacing one of the full adders with an approximation circuit with an error in only 1-2% of input cases. We also analysed and compared the delays of the approximate multiplier with that of an accurate multiplier. Further, we conceptualized fast and efficient error recovery techniques for this circuit for error intolerant systems.

  • Energy Efficient Adder

    Under the guidance of Prof. Smruti Ranjan Sarangi, we worked to build an approximate and fast adder which could be used in high performance systems by exploiting the accuracy-speed trade-off.

    We modified the Carry Look Ahead adder to get a smooth Error Curve by using faster transistors in part of the circuit producing most significant bits and slower transistors in the part producing least significant bits so that the total energy consumption remains same. We were able to achieve significant power savings with only a limited amount of error by using the adder at reduced clock period.